From patchwork Wed Apr 10 23:10:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1083685 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="phgnm8pH"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="Pe0MZN1I"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44fgDj0PZ8z9s47 for ; Thu, 11 Apr 2019 09:22:45 +1000 (AEST) Received: from localhost ([127.0.0.1]:39054 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEMYF-0001T2-1T for incoming@patchwork.ozlabs.org; Wed, 10 Apr 2019 19:22:43 -0400 Received: from eggs.gnu.org ([209.51.188.92]:43558) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEMVA-0007jM-1X for qemu-devel@nongnu.org; Wed, 10 Apr 2019 19:19:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hEMNq-0001iJ-Tp for qemu-devel@nongnu.org; Wed, 10 Apr 2019 19:12:01 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:29481) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hEMNg-0000yF-Cl; Wed, 10 Apr 2019 19:11:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1554937908; x=1586473908; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=+5E3HuMPpgPWZVNHr7cnMoYJBKKTpSGQ9wDj3jayeAA=; b=phgnm8pH1fmVuSKcdRlVk1GYxGKflZcuyoz8XRQNVhh43PmvkrLwsrQ/ dw9tN1a3ePtUKqyV2yZgmCIudoHTowudMJ5gSYknYyaVswL+oKaGcvEd4 5kfXmPQzr4xm58lfPjMHPjJBpQDtrQFmmSn3OO8DbGbDPy68rhSy6HHJA vuTq+jeRu6k3WNMXoSudywkTWmGGD1iEXjrMbAHP4/c4LaF9vypYb3mUL 1sWHQgj1NPSWbjr/ijAF/wpRgbhWsSE3hKGifTd9lCfuuQmrbFTDV/E+X IvbYoT+ipqnl3VIJ5JcHkYlGCsbJWEX1eS6HJdmMYH/Wbual9T0h55lke Q==; X-IronPort-AV: E=Sophos;i="5.60,335,1549900800"; d="scan'208";a="107205876" Received: from mail-sn1nam02lp2052.outbound.protection.outlook.com (HELO NAM02-SN1-obe.outbound.protection.outlook.com) ([104.47.36.52]) by ob1.hgst.iphmx.com with ESMTP; 11 Apr 2019 07:10:27 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector1-wdc-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+5E3HuMPpgPWZVNHr7cnMoYJBKKTpSGQ9wDj3jayeAA=; b=Pe0MZN1IL39k7KBLQO2+YGolx+tk5alt4s6SsZlZNpg4hu1opAKrrjDJDwB+BUCObycLZfeS4eE37ZEHKL0Z2xrKnmIF2F1wAiO1uL27m00uGftbOu7CRoEKujZkGlrK9MyXDlPt0naRM1gTQPkE65oRUCYDq44p0md5MFy6Mi0= Received: from BYAPR04MB4901.namprd04.prod.outlook.com (52.135.232.206) by BYAPR04MB5334.namprd04.prod.outlook.com (20.178.50.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1771.21; Wed, 10 Apr 2019 23:10:25 +0000 Received: from BYAPR04MB4901.namprd04.prod.outlook.com ([fe80::44e8:bd21:17b:348c]) by BYAPR04MB4901.namprd04.prod.outlook.com ([fe80::44e8:bd21:17b:348c%4]) with mapi id 15.20.1771.021; Wed, 10 Apr 2019 23:10:25 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" Thread-Topic: [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU Thread-Index: AQHU7/KUeywJFduBUU2FCQ0yom2eQA== Date: Wed, 10 Apr 2019 23:10:25 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.21.0 x-clientproxiedby: BY5PR13CA0023.namprd13.prod.outlook.com (2603:10b6:a03:180::36) To BYAPR04MB4901.namprd04.prod.outlook.com (2603:10b6:a03:4f::14) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alistair.Francis@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [199.255.44.250] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: de7438ed-fb20-43a8-0696-08d6be09b6b6 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:BYAPR04MB5334; x-ms-traffictypediagnostic: BYAPR04MB5334: wdcipoutbound: EOP-TRUE x-microsoft-antispam-prvs: x-forefront-prvs: 00032065B2 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(346002)(366004)(396003)(39860400002)(136003)(376002)(189003)(199004)(99286004)(11346002)(8936002)(14454004)(2616005)(6486002)(305945005)(6436002)(478600001)(97736004)(14444005)(446003)(71190400001)(118296001)(2501003)(66066001)(476003)(4326008)(256004)(44832011)(71200400001)(486006)(86362001)(102836004)(186003)(36756003)(81156014)(72206003)(3846002)(8676002)(25786009)(386003)(6506007)(5660300002)(53936002)(7736002)(50226002)(106356001)(105586002)(2906002)(68736007)(6116002)(54906003)(26005)(316002)(6512007)(81166006)(110136005)(52116002)(76176011); DIR:OUT; SFP:1102; SCL:1; SRVR:BYAPR04MB5334; H:BYAPR04MB4901.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: s5Agq2vgv8Xt0/VsHQgMIP1iaN22Gl2OgDPeoOLsDpW4VG7X4WF4SfOHoajlvbcgWn8nGFU1Y8rhD0fWKNOqFT8TWaYMhYVYWT2J3lXJbWnLBeee95UUv1b6Bl/5CFvfvbppRpym1Ei+s4TXKXCOXNqnNeJDlJ6ENGW1SZR1XU+YasHHkkeFftWt1qSqg77Dvtlv2TQ/WdP0LLeAv6WxAjfhFQQvHtT4Wndhb2T5tHhNZSsW3TB1qt95nkU34O7ZZCaSZPnytZf/JqcF3NFmhxquXLcIXdkSIOVb4oGWQENE3uUs6wR85r+XABM/cU+GBGjtdX0cgicwH01tDWqQFWVSyOsPXRMZgKoFJmX+kQuCVU8cMzIX8Hm/jIDMTgCBnJh0IUJnoKFV9ZzYLDgIOKv3ziLPnpU7QTyHqDFsKq4= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: de7438ed-fb20-43a8-0696-08d6be09b6b6 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2019 23:10:25.1631 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR04MB5334 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.154.45 Subject: [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , "palmer@sifive.com" , Alistair Francis , "ijc@hellion.org.uk" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" If a user specifies a CPU that we don't understand then we want to fall back to a CPU generated from the ISA string. At the moment the generated CPU is assumed to be a privledge spec version 1.10 CPU with an MMU. This can be changed in the future. Signed-off-by: Alistair Francis --- v3: - Ensure a minimal length so we don't run off the end of the string. - Don't parse the rv32/rv64 in the loop target/riscv/cpu.c | 101 ++++++++++++++++++++++++++++++++++++++++++++- target/riscv/cpu.h | 2 + 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d61bce6d55..27be9e412a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "exec/exec-all.h" #include "qapi/error.h" @@ -103,6 +104,99 @@ static void set_resetvec(CPURISCVState *env, int resetvec) #endif } +static void riscv_generate_cpu_init(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); + const char *riscv_cpu = mcc->isa_str; + target_ulong target_misa = 0; + target_ulong rvxlen = 0; + int i; + bool valid = false; + + /* + * We need at least 5 charecters for the string to be valid. Check that + * now so we can be lazier later. + */ + if (strlen(riscv_cpu) < 5) { + error_report("'%s' does not appear to be a valid RISC-V ISA string", + riscv_cpu); + exit(1); + } + + if (riscv_cpu[0] == 'r' && riscv_cpu[1] == 'v') { + /* Starts with "rv" */ + if (riscv_cpu[2] == '3' && riscv_cpu[3] == '2') { + valid = true; + rvxlen = RV32; + } + if (riscv_cpu[2] == '6' && riscv_cpu[3] == '4') { + valid = true; + rvxlen = RV64; + } + } + + if (!valid) { + error_report("'%s' does not appear to be a valid RISC-V CPU", + riscv_cpu); + exit(1); + } + + for (i = 4; i < strlen(riscv_cpu); i++) { + switch (riscv_cpu[i]) { + case 'i': + if (target_misa & RVE) { + error_report("I and E extensions are incompatible"); + exit(1); + } + target_misa |= RVI; + continue; + case 'e': + if (target_misa & RVI) { + error_report("I and E extensions are incompatible"); + exit(1); + } + target_misa |= RVE; + continue; + case 'g': + target_misa |= RVI | RVM | RVA | RVF | RVD; + continue; + case 'm': + target_misa |= RVM; + continue; + case 'a': + target_misa |= RVA; + continue; + case 'f': + target_misa |= RVF; + continue; + case 'd': + target_misa |= RVD; + continue; + case 'c': + target_misa |= RVC; + continue; + case 's': + target_misa |= RVS; + continue; + case 'u': + target_misa |= RVU; + continue; + default: + warn_report("QEMU does not support the %c extension", + riscv_cpu[i]); + continue; + } + } + + set_misa(env, rvxlen | target_misa); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_MMU); + set_feature(env, RISCV_FEATURE_PMP); +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -178,6 +272,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; + RISCVCPUClass *mcc; char *typename; char **cpuname; @@ -188,7 +283,10 @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) g_free(typename); if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || object_class_is_abstract(oc)) { - return NULL; + /* No CPU found, try the generic CPU and pass in the ISA string */ + oc = object_class_by_name(TYPE_RISCV_CPU_GEN); + mcc = RISCV_CPU_CLASS(oc); + mcc->isa_str = g_strdup(cpu_model); } return oc; } @@ -440,6 +538,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .class_init = riscv_cpu_class_init, }, DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_GEN, riscv_generate_cpu_init), #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 20bce8742e..453108a855 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -48,6 +48,7 @@ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_GEN RISCV_CPU_TYPE_NAME("rv*") #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") @@ -211,6 +212,7 @@ typedef struct RISCVCPUClass { /*< public >*/ DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + const char *isa_str; } RISCVCPUClass; /**