From patchwork Thu Dec 11 02:20:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hu Tao X-Patchwork-Id: 419924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4290814009B for ; Thu, 11 Dec 2014 13:27:06 +1100 (AEDT) Received: from localhost ([::1]:48791 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XytT6-0000hg-G3 for incoming@patchwork.ozlabs.org; Wed, 10 Dec 2014 21:27:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XytQE-00051W-VW for qemu-devel@nongnu.org; Wed, 10 Dec 2014 21:24:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XytQ5-0004Ut-UQ for qemu-devel@nongnu.org; Wed, 10 Dec 2014 21:24:06 -0500 Received: from [59.151.112.132] (port=26112 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XytQ5-0004T3-Ie for qemu-devel@nongnu.org; Wed, 10 Dec 2014 21:23:57 -0500 X-IronPort-AV: E=Sophos;i="5.04,848,1406563200"; d="scan'208";a="44842765" Received: from unknown (HELO edo.cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 11 Dec 2014 10:20:33 +0800 Received: from G08CNEXCHPEKD01.g08.fujitsu.local (localhost.localdomain [127.0.0.1]) by edo.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id sBB2NT6X025274; Thu, 11 Dec 2014 10:23:29 +0800 Received: from localhost.localdomain (10.167.226.102) by G08CNEXCHPEKD01.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.181.6; Thu, 11 Dec 2014 10:24:00 +0800 From: Hu Tao To: Date: Thu, 11 Dec 2014 10:20:24 +0800 Message-ID: X-Mailer: git-send-email 1.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.226.102] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Cc: Marcel Apfelbaum , "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v3 2/6] pci: introduce pci_host_config_enabled() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This makes code more readable. Signed-off-by: Hu Tao Reviewed-by: Marcel Apfelbaum --- hw/mips/gt64xxx_pci.c | 4 ++-- hw/pci/pci_host.c | 5 +++-- include/hw/pci/pci_host.h | 5 +++++ 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 1f2fe5f..f118c9c 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -564,7 +564,7 @@ static void gt64120_writel (void *opaque, hwaddr addr, if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { val = bswap32(val); } - if (phb->config_reg & (1u << 31)) { + if (pci_host_config_enabled(phb)) { pci_data_write(phb->bus, phb->config_reg, val, 4); } break; @@ -804,7 +804,7 @@ static uint64_t gt64120_readl (void *opaque, val = phb->config_reg; break; case GT_PCI0_CFGDATA: - if (!(phb->config_reg & (1 << 31))) { + if (!pci_host_config_enabled(phb)) { val = 0xffffffff; } else { val = pci_data_read(phb->bus, phb->config_reg, 4); diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 3e26f92..9bc47d8 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -133,8 +133,9 @@ static void pci_host_data_write(void *opaque, hwaddr addr, PCIHostState *s = opaque; PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n", addr, len, (unsigned)val); - if (s->config_reg & (1u << 31)) + if (pci_host_config_enabled(s)) { pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); + } } static uint64_t pci_host_data_read(void *opaque, @@ -142,7 +143,7 @@ static uint64_t pci_host_data_read(void *opaque, { PCIHostState *s = opaque; uint32_t val; - if (!(s->config_reg & (1U << 31))) { + if (!pci_host_config_enabled(s)) { return 0xffffffff; } val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index ba31595..b48791d 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -65,6 +65,11 @@ uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len); +static inline bool pci_host_config_enabled(struct PCIHostState *pci_host) +{ + return pci_host->config_reg & (1U << 31); +} + extern const MemoryRegionOps pci_host_conf_le_ops; extern const MemoryRegionOps pci_host_conf_be_ops; extern const MemoryRegionOps pci_host_data_le_ops;