From patchwork Wed Apr 3 05:17:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 233235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 964B32C0091 for ; Wed, 3 Apr 2013 16:18:47 +1100 (EST) Received: from localhost ([::1]:41022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNG5t-0000Vi-OX for incoming@patchwork.ozlabs.org; Wed, 03 Apr 2013 01:18:45 -0400 Received: from eggs.gnu.org ([208.118.235.92]:38695) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNG5V-0000IX-5h for qemu-devel@nongnu.org; Wed, 03 Apr 2013 01:18:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNG5T-0002A1-OK for qemu-devel@nongnu.org; Wed, 03 Apr 2013 01:18:21 -0400 Received: from mail-pb0-f44.google.com ([209.85.160.44]:41354) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNG5T-00029o-GQ for qemu-devel@nongnu.org; Wed, 03 Apr 2013 01:18:19 -0400 Received: by mail-pb0-f44.google.com with SMTP id wz12so645897pbc.17 for ; Tue, 02 Apr 2013 22:18:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:mime-version :content-type:content-transfer-encoding:x-gm-message-state; bh=r1iaMvOTXEVxJBOmRqss2kbrw2TTeIWbrpfFGRrwt/M=; b=f4fZtPQAG1sxSO/tk6SPoh7DeyQMK9NhE7IG1k78GBrkYLzGm7bBMFGE4Q/BaA8oGK 1bSl4V52Ubize9UICnahskLH2U5OCF3y+5QkMq1Jj+bVEornsCxpRjwpRcy2HdZ5XE9L nmPs5vcDZCS9bBEgQumW842vtA1ZXe6VGkC51HgIB1Wof5n9MpI9VTuPQEv8Is4Clh5M +6FNWGt7y7mQMi5jn/oSvVltP9FLRTC0BEnWdEu0D0CnjtXJ8AtqRZzoRbyXVEVoS5Xa Tl2PCWTO226HG4NyxO93oo8joFvlT/qOwCEROCbgVfreMYo2OMeeDZZD+WBd2E0sWi7u NgMA== X-Received: by 10.66.27.105 with SMTP id s9mr1097959pag.108.1364966298699; Tue, 02 Apr 2013 22:18:18 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id oq3sm5297817pac.16.2013.04.02.22.18.16 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 02 Apr 2013 22:18:17 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com Date: Wed, 3 Apr 2013 15:17:01 +1000 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlvQMU+DbTti1ylAaWrIbnop/0yEc914u4V5eUCufR2r71APYbnAKDvMrzkEhk9mx/P/pmJ X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.44 Cc: Peter Crosthwaite Subject: [Qemu-devel] [PATCH v5 01/16] xilinx_axienet: typedef XilinxAXIEnet struct X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Typedef xilinx_axienets object state struct to shorten the repeated usages of struct XilinxAXIEnet. Signed-off-by: Peter Crosthwaite Reviewed-by: Andreas Färber Acked-by: Edgar E. Iglesias --- hw/xilinx_axienet.c | 44 +++++++++++++++++++++++--------------------- 1 files changed, 23 insertions(+), 21 deletions(-) diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c index 5785290..c3c0663 100644 --- a/hw/xilinx_axienet.c +++ b/hw/xilinx_axienet.c @@ -306,6 +306,8 @@ struct TEMAC { void *parent; }; +typedef struct XilinxAXIEnet XilinxAXIEnet; + struct XilinxAXIEnet { SysBusDevice busdev; MemoryRegion iomem; @@ -365,37 +367,37 @@ struct XilinxAXIEnet { uint8_t *rxmem; }; -static void axienet_rx_reset(struct XilinxAXIEnet *s) +static void axienet_rx_reset(XilinxAXIEnet *s) { s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; } -static void axienet_tx_reset(struct XilinxAXIEnet *s) +static void axienet_tx_reset(XilinxAXIEnet *s) { s->tc = TC_JUM | TC_TX | TC_VLAN; } -static inline int axienet_rx_resetting(struct XilinxAXIEnet *s) +static inline int axienet_rx_resetting(XilinxAXIEnet *s) { return s->rcw[1] & RCW1_RST; } -static inline int axienet_rx_enabled(struct XilinxAXIEnet *s) +static inline int axienet_rx_enabled(XilinxAXIEnet *s) { return s->rcw[1] & RCW1_RX; } -static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s) +static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) { return !!(s->regs[R_RAF] & RAF_EMCF_EN); } -static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s) +static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) { return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); } -static void axienet_reset(struct XilinxAXIEnet *s) +static void axienet_reset(XilinxAXIEnet *s) { axienet_rx_reset(s); axienet_tx_reset(s); @@ -406,7 +408,7 @@ static void axienet_reset(struct XilinxAXIEnet *s) s->emmc = EMMC_LINKSPEED_100MB; } -static void enet_update_irq(struct XilinxAXIEnet *s) +static void enet_update_irq(XilinxAXIEnet *s) { s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; qemu_set_irq(s->irq, !!s->regs[R_IP]); @@ -414,7 +416,7 @@ static void enet_update_irq(struct XilinxAXIEnet *s) static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) { - struct XilinxAXIEnet *s = opaque; + XilinxAXIEnet *s = opaque; uint32_t r = 0; addr >>= 2; @@ -506,7 +508,7 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) static void enet_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - struct XilinxAXIEnet *s = opaque; + XilinxAXIEnet *s = opaque; struct TEMAC *t = &s->TEMAC; addr >>= 2; @@ -618,7 +620,7 @@ static const MemoryRegionOps enet_ops = { static int eth_can_rx(NetClientState *nc) { - struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc); + XilinxAXIEnet *s = qemu_get_nic_opaque(nc); /* RX enabled? */ return !axienet_rx_resetting(s) && axienet_rx_enabled(s); @@ -641,7 +643,7 @@ static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) { - struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc); + XilinxAXIEnet *s = qemu_get_nic_opaque(nc); static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; @@ -786,7 +788,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) static void eth_cleanup(NetClientState *nc) { /* FIXME. */ - struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc); + XilinxAXIEnet *s = qemu_get_nic_opaque(nc); g_free(s->rxmem); g_free(s); } @@ -794,7 +796,7 @@ static void eth_cleanup(NetClientState *nc) static void axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr) { - struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); + XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); /* TX enable ? */ if (!(s->tc & TC_TX)) { @@ -844,7 +846,7 @@ static NetClientInfo net_xilinx_enet_info = { static int xilinx_enet_init(SysBusDevice *dev) { - struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev); + XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev); sysbus_init_irq(dev, &s->irq); @@ -869,7 +871,7 @@ static int xilinx_enet_init(SysBusDevice *dev) static void xilinx_enet_initfn(Object *obj) { - struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); + XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); Error *errp = NULL; object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, @@ -878,10 +880,10 @@ static void xilinx_enet_initfn(Object *obj) } static Property xilinx_enet_properties[] = { - DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7), - DEFINE_PROP_UINT32("rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000), - DEFINE_PROP_UINT32("txmem", struct XilinxAXIEnet, c_txmem, 0x1000), - DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf), + DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), + DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), + DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), + DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), DEFINE_PROP_END_OF_LIST(), }; @@ -899,7 +901,7 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data) static const TypeInfo xilinx_enet_info = { .name = "xlnx.axi-ethernet", .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(struct XilinxAXIEnet), + .instance_size = sizeof(XilinxAXIEnet), .class_init = xilinx_enet_class_init, .instance_init = xilinx_enet_initfn, .interfaces = (InterfaceInfo[]) {