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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id m8-20020adfa3c8000000b0032d7fde2d3csm7990663wrb.79.2023.10.13.00.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:50:41 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org Cc: Emmanouil Pitsidianakis , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [RFC PATCH 27/78] target/riscv: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:47:31 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- target/riscv/insn_trans/trans_rvi.c.inc | 2 +- target/riscv/insn_trans/trans_rvzce.c.inc | 22 +++++++++++----------- target/riscv/translate.c | 4 ++-- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 25cb60558a..98dd2e3cf6 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -89,61 +89,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) static TCGCond gen_compare_i128(bool bz, TCGv rl, TCGv al, TCGv ah, TCGv bl, TCGv bh, TCGCond cond) { TCGv rh = tcg_temp_new(); bool invert = false; switch (cond) { case TCG_COND_EQ: case TCG_COND_NE: if (bz) { tcg_gen_or_tl(rl, al, ah); } else { tcg_gen_xor_tl(rl, al, bl); tcg_gen_xor_tl(rh, ah, bh); tcg_gen_or_tl(rl, rl, rh); } break; case TCG_COND_GE: case TCG_COND_LT: if (bz) { tcg_gen_mov_tl(rl, ah); } else { TCGv tmp = tcg_temp_new(); tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh); tcg_gen_xor_tl(rl, rh, ah); tcg_gen_xor_tl(tmp, ah, bh); tcg_gen_and_tl(rl, rl, tmp); tcg_gen_xor_tl(rl, rh, rl); } break; case TCG_COND_LTU: invert = true; - /* fallthrough */ + fallthrough; case TCG_COND_GEU: { TCGv tmp = tcg_temp_new(); TCGv zero = tcg_constant_tl(0); TCGv one = tcg_constant_tl(1); cond = TCG_COND_NE; /* borrow in to second word */ tcg_gen_setcond_tl(TCG_COND_LTU, tmp, al, bl); /* seed third word with 1, which will be result */ tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero); tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero); } break; default: g_assert_not_reached(); } if (invert) { cond = tcg_invert_cond(cond); } return cond; } diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index 2d992e14c4..f0bcbb4f72 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -116,52 +116,52 @@ static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist) { uint32_t reg_bitmap = 0; if (has_ext(ctx, RVE) && rlist > 6) { return 0; } switch (rlist) { case 15: reg_bitmap |= 1 << (X_Sn + 11) ; reg_bitmap |= 1 << (X_Sn + 10) ; - /* FALL THROUGH */ + fallthrough; case 14: reg_bitmap |= 1 << (X_Sn + 9) ; - /* FALL THROUGH */ + fallthrough; case 13: reg_bitmap |= 1 << (X_Sn + 8) ; - /* FALL THROUGH */ + fallthrough; case 12: reg_bitmap |= 1 << (X_Sn + 7) ; - /* FALL THROUGH */ + fallthrough; case 11: reg_bitmap |= 1 << (X_Sn + 6) ; - /* FALL THROUGH */ + fallthrough; case 10: reg_bitmap |= 1 << (X_Sn + 5) ; - /* FALL THROUGH */ + fallthrough; case 9: reg_bitmap |= 1 << (X_Sn + 4) ; - /* FALL THROUGH */ + fallthrough; case 8: reg_bitmap |= 1 << (X_Sn + 3) ; - /* FALL THROUGH */ + fallthrough; case 7: reg_bitmap |= 1 << (X_Sn + 2) ; - /* FALL THROUGH */ + fallthrough; case 6: reg_bitmap |= 1 << X_S1 ; - /* FALL THROUGH */ + fallthrough; case 5: reg_bitmap |= 1 << X_S0; - /* FALL THROUGH */ + fallthrough; case 4: reg_bitmap |= 1 << xRA; break; default: break; } return reg_bitmap; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb16..c99e513221 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -431,26 +431,26 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) { if (!ctx->cfg_ptr->ext_zfinx) { return cpu_fpr[reg_num]; } if (reg_num == 0) { return tcg_constant_i64(0); } switch (get_xl(ctx)) { case MXL_RV32: #ifdef TARGET_RISCV32 { TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); return t; } #else - /* fall through */ + fallthrough; case MXL_RV64: return cpu_gpr[reg_num]; #endif default: g_assert_not_reached(); } } @@ -505,24 +505,24 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) { if (!ctx->cfg_ptr->ext_zfinx) { tcg_gen_mov_i64(cpu_fpr[reg_num], t); return; } if (reg_num != 0) { switch (get_xl(ctx)) { case MXL_RV32: #ifdef TARGET_RISCV32 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); break; #else - /* fall through */ + fallthrough; case MXL_RV64: tcg_gen_mov_i64(cpu_gpr[reg_num], t); break; #endif default: g_assert_not_reached(); } } }