From patchwork Thu May 28 05:37:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 478099 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1YxqVm-0002CS-5K for mharc-qemu-devel@gnu.org; Thu, 28 May 2015 01:37:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqVj-00028F-G1 for qemu-devel@nongnu.org; Thu, 28 May 2015 01:37:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxqVg-0006lQ-K5 for qemu-devel@nongnu.org; Thu, 28 May 2015 01:37:43 -0400 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]:32913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqVg-0006ka-8S for qemu-devel@nongnu.org; Thu, 28 May 2015 01:37:40 -0400 Received: by padbw4 with SMTP id bw4so15170161pad.0 for ; Wed, 27 May 2015 22:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=B16rooVCLtAlApgzVGM0Ec9CC+Ivvp2RqUBNrRAtWts=; b=x3TkfxfFA5apaE1kV8aEZ1f1WXKC++TpmtpElhTMMc83xeK/iuHyoqdqgellq9MN0J nyDozsHUtjg7s65sXtEws58ZBi/9DZQtm+y44ZhHzCVBYD5EPhVQrTd8Oxs//VvTlvYE /0l6fZaxntVdQCG2WMaEbQcFmqLGJufciMP5CF8B/Up/tWV8krFimOiZSjZmduG5VQk6 jWDEjA/JTRBNBtfBxX71yJ1H8Eo8tkYrkslz5NC7f3cQEC3slCvObZwFiCJV7fluNIZK ILXMQw9O0cFUV5nOH/sA5eJFmyfSlVOdD+JroOpymYn2Y5r2xpMIviBEL/a+vbkqAIM5 xWwQ== X-Received: by 10.70.49.168 with SMTP id v8mr2297960pdn.24.1432791459552; Wed, 27 May 2015 22:37:39 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id f8sm962149pas.10.2015.05.27.22.37.38 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Wed, 27 May 2015 22:37:38 -0700 (PDT) Sender: Alistair Francis From: Alistair Francis To: qemu-devel@nongnu.org, edgar.iglesias@xilinx.com Date: Thu, 28 May 2015 15:37:03 +1000 Message-Id: X-Mailer: git-send-email 2.1.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::235 Cc: peter.crosthwaite@xilinx.com, rth@twiddle.net, afaerber@suse.de, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v2 2/5] target-microblaze: Preserve the pvr registers during reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 May 2015 05:37:44 -0000 Move the Microblaze PVR registers to the end of the CPUMBState and preserve them during reset. This is similar to what the QEMU ARM model does with some of it's registers. This allows the Microblaze PVR registers to only be set once at realise instead of constantly at reset. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Reviewed-by: Edgar E. Iglesias --- V2: - Remove the memset and cpu_reset functions as they aren't required in the realize and I'm touching them anyway. NOTE: The individual machine resets still write to the PVR registers on each reset. This is no longer required as it only needs to be done once. Instead of moving them now, they are being left there and will be removed when they are all converted to the standard CPU properties. target-microblaze/cpu.c | 40 ++++++++++++++++++++++------------------ target-microblaze/cpu.h | 10 ++++++---- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 67e3182..95be540 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -63,13 +63,34 @@ static void mb_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, sizeof(CPUMBState)); + memset(env, 0, offsetof(CPUMBState, pvr)); env->res_addr = RES_ADDR_NONE; tlb_flush(s, 1); /* Disable stack protector. */ env->shr = ~0; +#if defined(CONFIG_USER_ONLY) + /* start in user mode with interrupts enabled. */ + env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; +#else + env->sregs[SR_MSR] = 0; + mmu_init(&env->mmu); + env->mmu.c_mmu = 3; + env->mmu.c_mmu_tlb_access = 3; + env->mmu.c_mmu_zones = 16; +#endif +} + +static void mb_cpu_realizefn(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + + qemu_init_vcpu(cs); + env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ | PVR0_USE_BARREL_MASK \ | PVR0_USE_DIV_MASK \ @@ -99,25 +120,8 @@ static void mb_cpu_reset(CPUState *s) env->sregs[SR_PC] = cpu->base_vectors; #if defined(CONFIG_USER_ONLY) - /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ -#else - env->sregs[SR_MSR] = 0; - mmu_init(&env->mmu); - env->mmu.c_mmu = 3; - env->mmu.c_mmu_tlb_access = 3; - env->mmu.c_mmu_zones = 16; #endif -} - -static void mb_cpu_realizefn(DeviceState *dev, Error **errp) -{ - CPUState *cs = CPU(dev); - MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); - - cpu_reset(cs); - qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); } diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 4ea04ac..e4c1cde 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -260,16 +260,18 @@ struct CPUMBState { #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) uint32_t iflags; - struct { - uint32_t regs[16]; - } pvr; - #if !defined(CONFIG_USER_ONLY) /* Unified MMU. */ struct microblaze_mmu mmu; #endif CPU_COMMON + + /* These fields are preserved on reset. */ + + struct { + uint32_t regs[16]; + } pvr; }; #include "cpu-qom.h"