From patchwork Tue Sep 13 19:52:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 1677492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MRvPn0j4Xz1ynx for ; Wed, 14 Sep 2022 05:57:17 +1000 (AEST) Received: from localhost ([::1]:42098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYC1y-0000jh-Vk for incoming@patchwork.ozlabs.org; Tue, 13 Sep 2022 15:57:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYBxY-0001Zw-JY; Tue, 13 Sep 2022 15:52:40 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:12573) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYBxW-00052e-OJ; Tue, 13 Sep 2022 15:52:40 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 31A0674637F; Tue, 13 Sep 2022 21:52:37 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id ED14E74632B; Tue, 13 Sep 2022 21:52:36 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM MIME-Version: 1.0 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 21:52:36 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To allow removing the do_init hack we need to improve the DDR2 SDRAM controller model to handle the enable/disable bit that it ignored so far. Signed-off-by: BALATON Zoltan --- v2: replace 0x08000000 with BIT(27) hw/ppc/ppc440_uc.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 01184e717b..3c442eaecc 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -23,6 +23,7 @@ #include "sysemu/reset.h" #include "ppc440.h" #include "qom/object.h" +#include "trace.h" /*****************************************************************************/ /* L2 Cache as SRAM */ @@ -484,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env) /* SDRAM controller */ typedef struct ppc440_sdram_t { uint32_t addr; + uint32_t mcopt2; int nbanks; Ppc4xxSdramBank bank[4]; } ppc440_sdram_t; @@ -581,12 +583,15 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int i, { if (sdram->bank[i].bcr & 1) { /* First unmap RAM if enabled */ + trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), + sdram_size(sdram->bank[i].bcr)); sdram_bank_unmap(&sdram->bank[i]); } sdram->bank[i].bcr = bcr & 0xffe0ffc1; sdram->bank[i].base = sdram_base(bcr); sdram->bank[i].size = sdram_size(bcr); if (enabled && (bcr & 1)) { + trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); sdram_bank_map(&sdram->bank[i]); } } @@ -596,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram) int i; for (i = 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size != 0) { + if (sdram->bank[i].size) { sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, sdram->bank[i].size), 1); } else { @@ -605,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram) } } +static void sdram_unmap_bcr(ppc440_sdram_t *sdram) +{ + int i; + + for (i = 0; i < sdram->nbanks; i++) { + if (sdram->bank[i].size) { + sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); + } + } +} + static uint32_t dcr_read_sdram(void *opaque, int dcrn) { ppc440_sdram_t *sdram = opaque; @@ -636,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) ret = 0x80000000; break; case 0x21: /* SDRAM_MCOPT2 */ - ret = 0x08000000; + ret = sdram->mcopt2; break; case 0x40: /* SDRAM_MB0CF */ ret = 0x00008001; @@ -680,6 +696,19 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) switch (sdram->addr) { case 0x00: /* B0CR */ break; + case 0x21: /* SDRAM_MCOPT2 */ + if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) { + trace_ppc4xx_sdram_enable("enable"); + /* validate all RAM mappings */ + sdram_map_bcr(sdram); + sdram->mcopt2 |= BIT(27); + } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) { + trace_ppc4xx_sdram_enable("disable"); + /* invalidate all RAM mappings */ + sdram_unmap_bcr(sdram); + sdram->mcopt2 &= ~BIT(27); + } + break; default: break; } @@ -694,6 +723,7 @@ static void sdram_reset(void *opaque) ppc440_sdram_t *sdram = opaque; sdram->addr = 0; + sdram->mcopt2 = BIT(27); } void ppc440_sdram_init(CPUPPCState *env, int nbanks,