From patchwork Sat Jul 18 09:40:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 497346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 061D6140D4D for ; Sat, 18 Jul 2015 19:47:36 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=W+cBthn6; dkim-atps=neutral Received: from localhost ([::1]:47660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZGOiT-00028u-Vo for incoming@patchwork.ozlabs.org; Sat, 18 Jul 2015 05:47:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41120) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZGOcd-0007Sm-Bf for qemu-devel@nongnu.org; Sat, 18 Jul 2015 05:41:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZGOca-0004e4-4Y for qemu-devel@nongnu.org; Sat, 18 Jul 2015 05:41:31 -0400 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]:33636) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZGOcZ-0004dy-Uc for qemu-devel@nongnu.org; Sat, 18 Jul 2015 05:41:28 -0400 Received: by padck2 with SMTP id ck2so73394612pad.0 for ; Sat, 18 Jul 2015 02:41:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=hhXkwIRW6otgtabBAiJxqxm2esdQWqPlMySPw3B9sNA=; b=W+cBthn6kr890tQliueVlaw5Q/x6p4wIhfVmt7fy/iR4e9SztThy355fbquGAvxLIq DyR9XWuOAXqU8dGD1tmwkHpEsmBZJz5F5ui7Ag84phdpgKst9JCXxadM2P5xR9InD/gq 8uicYribdHh3wcxj1hz7rMTO4VUOeit+BXL33MV55GRHEueuU838Z4Mndq27WG0lHoQI MbMGGBM2jnMciANgbzyKvD+FXOpvemkMGZ9bSnK2cR2O7gONSle01OFpxy5x0iiPetQ/ +Kp28oG7DuZTcQetq6Lh+3t3gL8hlvRVyFXEKalV5GzuJvwjFbz7YkZeLP2Mapiio574 Q/jg== X-Received: by 10.68.246.1 with SMTP id xs1mr37744415pbc.53.1437212487230; Sat, 18 Jul 2015 02:41:27 -0700 (PDT) Received: from pcrost-box.hsd1.ca.comcast.net (c-73-15-58-35.hsd1.ca.comcast.net. [73.15.58.35]) by smtp.gmail.com with ESMTPSA id j5sm8460034pdi.7.2015.07.18.02.41.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 18 Jul 2015 02:41:26 -0700 (PDT) From: Peter Crosthwaite X-Google-Original-From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Sat, 18 Jul 2015 02:40:21 -0700 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22d Cc: peter.maydell@linaro.org, Peter Crosthwaite , edgar.iglesias@gmail.com, pbonzini@redhat.com, afaerber@suse.de, rth@twiddle.net Subject: [Qemu-devel] [PATCH v3 11/35] cputlb: move CPU_LOOP() for tlb_reset() to exec.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To prepare for multi-arch, cputlb should only have awareness of one single architecture. This means it should not have access to the full CPU lists which may be heterogeneous. Instead, push the CPU_LOOP() up to the one and only caller in exec.c. Signed-off-by: Peter Crosthwaite --- Easier reading with git diff -w Changed since RFCv2: split off to new patch (previously part of core virtualisation patch) --- cputlb.c | 27 ++++++++++++--------------- exec.c | 5 ++++- include/exec/cputlb.h | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/cputlb.c b/cputlb.c index a506086..4142382 100644 --- a/cputlb.c +++ b/cputlb.c @@ -165,27 +165,24 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) return ram_addr; } -void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length) +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) { - CPUState *cpu; CPUArchState *env; - CPU_FOREACH(cpu) { - int mmu_idx; + int mmu_idx; - env = cpu->env_ptr; - for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - unsigned int i; + env = cpu->env_ptr; + for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + unsigned int i; - for (i = 0; i < CPU_TLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], - start1, length); - } + for (i = 0; i < CPU_TLB_SIZE; i++) { + tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], + start1, length); + } - for (i = 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i], - start1, length); - } + for (i = 0; i < CPU_VTLB_SIZE; i++) { + tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i], + start1, length); } } } diff --git a/exec.c b/exec.c index e5101e0..fc7aba5 100644 --- a/exec.c +++ b/exec.c @@ -894,6 +894,7 @@ found: static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) { + CPUState *cpu; ram_addr_t start1; RAMBlock *block; ram_addr_t end; @@ -905,7 +906,9 @@ static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) block = qemu_get_ram_block(start); assert(block == qemu_get_ram_block(end - 1)); start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); - cpu_tlb_reset_dirty_all(start1, length); + CPU_FOREACH(cpu) { + tlb_reset_dirty(cpu, start1, length); + } rcu_read_unlock(); } diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 360815e..c3aaa30 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -25,7 +25,7 @@ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length); -void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); void tlb_set_dirty(CPUArchState *env, target_ulong vaddr); extern int tlb_flush_count;