From patchwork Sun Sep 14 08:18:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 389014 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1DFF91400B7 for ; Sun, 14 Sep 2014 18:19:06 +1000 (EST) Received: from localhost ([::1]:53285 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XT51U-0003dR-4e for incoming@patchwork.ozlabs.org; Sun, 14 Sep 2014 04:19:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50962) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XT50x-0002kg-Im for qemu-devel@nongnu.org; Sun, 14 Sep 2014 04:18:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XT50r-00089X-00 for qemu-devel@nongnu.org; Sun, 14 Sep 2014 04:18:31 -0400 Received: from mail-pd0-x235.google.com ([2607:f8b0:400e:c02::235]:44472) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XT50q-00089S-Ld for qemu-devel@nongnu.org; Sun, 14 Sep 2014 04:18:24 -0400 Received: by mail-pd0-f181.google.com with SMTP id w10so4240976pde.12 for ; Sun, 14 Sep 2014 01:18:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vk3guE6klml5NbXUuOp1eAwNS6GbgSyzpkTcru9a4oo=; b=DtP5lZSPtHGgAF/yRu84m9qUp1ot9o97492AfGt2+bqgviV90C6D6vQQtDnYfa0D6q fmq9Ix/wQqYYnyLOSRoAcmeGE/I56j2Z3LI2ZeHxYEaretDjfwhSXU/QpRZuq8/Z5QEW icmT7Yl9AaO6OdnGFbTLIEBRQ+3tm7RAgz91ZiuaQlzDFDUrpvYcGGciYHUpQd3eRST3 jI17Y3F1S5nhKg4JuG71L7vuGpkoD3rg3gcj/A7PgcpPc9iDPrkt1yzNEAfJydEzHNjR 3lAO0BupDXYZcdbd4fLRm8LYqvDysyNusPNRaFdhogNaRgMILGXH54bcd4uueXRqL0LV ob6g== X-Received: by 10.68.200.72 with SMTP id jq8mr28803164pbc.116.1410682703713; Sun, 14 Sep 2014 01:18:23 -0700 (PDT) Received: from localhost (123-243-147-200.static.tpgi.com.au. [123.243.147.200]) by mx.google.com with ESMTPSA id v1sm8212866pdp.76.2014.09.14.01.18.22 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 14 Sep 2014 01:18:23 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Sun, 14 Sep 2014 18:18:18 +1000 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::235 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, konstanty@ieee.org, martin.galvan@tallertechnologies.com Subject: [Qemu-devel] [Patch v1 1/8] stm32f205_timer: Add the stm32f205 Timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the stm32f205 timers: TIM2, TIM3, TIM4 and TIM5 to QEMU. Signed-off-by: Alistair Francis --- Changes from RFC: - Small changes to functionality and style. Thanks to Peter C - Rename to make the timer more generic - Split the config settings to device level default-configs/arm-softmmu.mak | 1 + hw/timer/Makefile.objs | 1 + hw/timer/stm32f205_timer.c | 305 +++++++++++++++++++++++++++++++++++++ include/hw/timer/stm32f205_timer.h | 97 ++++++++++++ 4 files changed, 404 insertions(+) create mode 100644 hw/timer/stm32f205_timer.c create mode 100644 include/hw/timer/stm32f205_timer.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index f3513fa..cf23b24 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -78,6 +78,7 @@ CONFIG_NSERIES=y CONFIG_REALVIEW=y CONFIG_ZAURUS=y CONFIG_ZYNQ=y +CONFIG_STM32F205_TIMER=y CONFIG_VERSATILE_PCI=y CONFIG_VERSATILE_I2C=y diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 2c86c3d..6c1661e 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -17,6 +17,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o common-obj-$(CONFIG_IMX) += imx_gpt.o common-obj-$(CONFIG_LM32) += lm32_timer.o common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o +common-obj-$(CONFIG_STM32F205_TIMER) += stm32f205_timer.o obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o diff --git a/hw/timer/stm32f205_timer.c b/hw/timer/stm32f205_timer.c new file mode 100644 index 0000000..c4a84eb --- /dev/null +++ b/hw/timer/stm32f205_timer.c @@ -0,0 +1,305 @@ +/* + * STM32F205 Timer + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw/timer/stm32f205_timer.h" + +#ifndef STM_TIMER_ERR_DEBUG +#define STM_TIMER_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (STM_TIMER_ERR_DEBUG >= lvl) { \ + qemu_log("stm32f205_timer: %s:" fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void stm32f205_timer_interrupt(void *opaque) +{ + STM32f205TimerState *s = opaque; + + DB_PRINT("Interrupt in: %s\n", __func__); + + if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { + s->tim_sr |= 1; + qemu_irq_pulse(s->irq); + } +} + +static void stm32f205_timer_set_alarm(STM32f205TimerState *s) +{ + uint32_t ticks; + int64_t now; + + DB_PRINT("Alarm raised in: %s at 0x%x\n", __func__, s->tim_cr1); + + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ticks = s->tim_arr - (s->tick_offset + (now / get_ticks_per_sec())) * + (s->tim_psc + 1); + + DB_PRINT("Alarm set in %d ticks\n", ticks); + + if (ticks == 0) { + timer_del(s->timer); + stm32f205_timer_interrupt(s); + } else { + timer_mod(s->timer, (now + (int64_t) ticks)); + DB_PRINT("Wait Time: %u\n", (uint32_t) (now + ticks)); + } +} + +static void stm32f205_timer_reset(DeviceState *dev) +{ + STM32f205TimerState *s = STM32F205TIMER(dev); + + s->tim_cr1 = 0; + s->tim_cr2 = 0; + s->tim_smcr = 0; + s->tim_dier = 0; + s->tim_sr = 0; + s->tim_egr = 0; + s->tim_ccmr1 = 0; + s->tim_ccmr2 = 0; + s->tim_ccer = 0; + s->tim_cnt = 0; + s->tim_psc = 0; + s->tim_arr = 0; + s->tim_ccr1 = 0; + s->tim_ccr2 = 0; + s->tim_ccr3 = 0; + s->tim_ccr4 = 0; + s->tim_dcr = 0; + s->tim_dmar = 0; + s->tim_or = 0; +} + +static uint64_t stm32f205_timer_read(void *opaque, hwaddr offset, + unsigned size) +{ + STM32f205TimerState *s = opaque; + + DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); + + switch (offset) { + case TIM_CR1: + return s->tim_cr1; + case TIM_CR2: + return s->tim_cr2; + case TIM_SMCR: + return s->tim_smcr; + case TIM_DIER: + return s->tim_dier; + case TIM_SR: + return s->tim_sr; + case TIM_EGR: + return s->tim_egr; + case TIM_CCMR1: + return s->tim_ccmr1; + case TIM_CCMR2: + return s->tim_ccmr2; + case TIM_CCER: + return s->tim_ccer; + case TIM_CNT: + return s->tim_cnt; + case TIM_PSC: + return s->tim_psc; + case TIM_ARR: + return s->tim_arr; + case TIM_CCR1: + return s->tim_ccr1; + case TIM_CCR2: + return s->tim_ccr2; + case TIM_CCR3: + return s->tim_ccr3; + case TIM_CCR4: + return s->tim_ccr4; + case TIM_DCR: + return s->tim_dcr; + case TIM_DMAR: + return s->tim_dmar; + case TIM_OR: + return s->tim_or; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F205_timer_write: Bad offset %x\n", (int) offset); + } + + return 0; +} + +static void stm32f205_timer_write(void *opaque, hwaddr offset, + uint64_t val64, unsigned size) +{ + STM32f205TimerState *s = opaque; + uint32_t value = val64; + + DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); + + switch (offset) { + case TIM_CR1: + s->tim_cr1 = value; + return; + case TIM_CR2: + s->tim_cr2 = value; + return; + case TIM_SMCR: + s->tim_smcr = value; + return; + case TIM_DIER: + s->tim_dier = value; + return; + case TIM_SR: + s->tim_sr &= value; + stm32f205_timer_set_alarm(s); + return; + case TIM_EGR: + s->tim_egr = value; + if (s->tim_egr & 1) { + /* Re-init the counter */ + stm32f205_timer_reset(DEVICE(s)); + } + return; + case TIM_CCMR1: + s->tim_ccmr1 = value; + return; + case TIM_CCMR2: + s->tim_ccmr2 = value; + return; + case TIM_CCER: + s->tim_ccer = value; + return; + case TIM_CNT: + s->tim_cnt = value; + stm32f205_timer_set_alarm(s); + return; + case TIM_PSC: + s->tim_psc = value; + return; + case TIM_ARR: + s->tim_arr = value; + stm32f205_timer_set_alarm(s); + return; + case TIM_CCR1: + s->tim_ccr1 = value; + return; + case TIM_CCR2: + s->tim_ccr2 = value; + return; + case TIM_CCR3: + s->tim_ccr3 = value; + return; + case TIM_CCR4: + s->tim_ccr4 = value; + return; + case TIM_DCR: + s->tim_dcr = value; + return; + case TIM_DMAR: + s->tim_dmar = value; + return; + case TIM_OR: + s->tim_or = value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F205_timer_write: Bad offset %x\n", (int) offset); + } +} + +static const MemoryRegionOps stm32f205_timer_ops = { + .read = stm32f205_timer_read, + .write = stm32f205_timer_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f205_timer_init(Object *obj) +{ + STM32f205TimerState *s = STM32F205TIMER(obj); + struct tm tm; + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->iomem, obj, &stm32f205_timer_ops, s, + "stm32f205_timer", 0x2000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + qemu_get_timedate(&tm, 0); + s->tick_offset = mktimegm(&tm) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec(); + + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f205_timer_interrupt, s); +} + +static const VMStateDescription vmstate_stm32f205_timer = { + .name = "stm32f205_timer", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(tick_offset_vmstate, STM32f205TimerState), + VMSTATE_UINT32(tim_cr1, STM32f205TimerState), + VMSTATE_UINT32(tim_cr2, STM32f205TimerState), + VMSTATE_UINT32(tim_smcr, STM32f205TimerState), + VMSTATE_UINT32(tim_dier, STM32f205TimerState), + VMSTATE_UINT32(tim_sr, STM32f205TimerState), + VMSTATE_UINT32(tim_egr, STM32f205TimerState), + VMSTATE_UINT32(tim_ccmr1, STM32f205TimerState), + VMSTATE_UINT32(tim_ccmr1, STM32f205TimerState), + VMSTATE_UINT32(tim_ccer, STM32f205TimerState), + VMSTATE_UINT32(tim_cnt, STM32f205TimerState), + VMSTATE_UINT32(tim_psc, STM32f205TimerState), + VMSTATE_UINT32(tim_arr, STM32f205TimerState), + VMSTATE_UINT32(tim_ccr1, STM32f205TimerState), + VMSTATE_UINT32(tim_ccr2, STM32f205TimerState), + VMSTATE_UINT32(tim_ccr3, STM32f205TimerState), + VMSTATE_UINT32(tim_ccr4, STM32f205TimerState), + VMSTATE_UINT32(tim_dcr, STM32f205TimerState), + VMSTATE_UINT32(tim_dmar, STM32f205TimerState), + VMSTATE_UINT32(tim_or, STM32f205TimerState), + VMSTATE_END_OF_LIST() + } +}; + +static void stm32f205_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_stm32f205_timer; + dc->reset = stm32f205_timer_reset; +} + +static const TypeInfo stm32f205_timer_info = { + .name = TYPE_STM32F205_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32f205TimerState), + .instance_init = stm32f205_timer_init, + .class_init = stm32f205_timer_class_init, +}; + +static void stm32f205_timer_register_types(void) +{ + type_register_static(&stm32f205_timer_info); +} + +type_init(stm32f205_timer_register_types) diff --git a/include/hw/timer/stm32f205_timer.h b/include/hw/timer/stm32f205_timer.h new file mode 100644 index 0000000..c26ae57 --- /dev/null +++ b/include/hw/timer/stm32f205_timer.h @@ -0,0 +1,97 @@ +/* + * STM32F205 Timer + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM_TIMER_H +#define HW_STM_TIMER_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" + +#define TIM_CR1 0x00 +#define TIM_CR2 0x04 +#define TIM_SMCR 0x08 +#define TIM_DIER 0x0C +#define TIM_SR 0x10 +#define TIM_EGR 0x14 +#define TIM_CCMR1 0x18 +#define TIM_CCMR2 0x1C +#define TIM_CCER 0x20 +#define TIM_CNT 0x24 +#define TIM_PSC 0x28 +#define TIM_ARR 0x2C +#define TIM_CCR1 0x34 +#define TIM_CCR2 0x38 +#define TIM_CCR3 0x3C +#define TIM_CCR4 0x40 +#define TIM_DCR 0x48 +#define TIM_DMAR 0x4C +#define TIM_OR 0x50 + +#define TIM_CR1_CEN 1 + +#define TIM_CCER_CC2E (1 << 4) +#define TIM_CCMR1_OC2M2 (1 << 14) +#define TIM_CCMR1_OC2M1 (1 << 13) + +#define TIM_DIER_UIE 1 + +#define TYPE_STM32F205_TIMER "stm32f205-timer" +#define STM32F205TIMER(obj) OBJECT_CHECK(STM32f205TimerState, \ + (obj), TYPE_STM32F205_TIMER) + +typedef struct STM32f205TimerState { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion iomem; + QEMUTimer *timer; + qemu_irq irq; + + uint32_t tick_offset_vmstate; + uint32_t tick_offset; + + uint32_t tim_cr1; + uint32_t tim_cr2; + uint32_t tim_smcr; + uint32_t tim_dier; + uint32_t tim_sr; + uint32_t tim_egr; + uint32_t tim_ccmr1; + uint32_t tim_ccmr2; + uint32_t tim_ccer; + uint32_t tim_cnt; + uint32_t tim_psc; + uint32_t tim_arr; + uint32_t tim_ccr1; + uint32_t tim_ccr2; + uint32_t tim_ccr3; + uint32_t tim_ccr4; + uint32_t tim_dcr; + uint32_t tim_dmar; + uint32_t tim_or; +} STM32f205TimerState; + +#endif