From patchwork Tue Jul 18 11:55:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 790192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=208.118.235.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xBdy45N2Vz9rxj for ; Tue, 18 Jul 2017 21:59:56 +1000 (AEST) Received: from localhost ([::1]:55778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXRAP-00067K-Iy for incoming@patchwork.ozlabs.org; Tue, 18 Jul 2017 07:59:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXR7L-0003t5-1T for qemu-devel@nongnu.org; Tue, 18 Jul 2017 07:56:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXR7I-0005FF-Un for qemu-devel@nongnu.org; Tue, 18 Jul 2017 07:56:43 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:3251) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXR7I-0005F4-LY for qemu-devel@nongnu.org; Tue, 18 Jul 2017 07:56:40 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 2433FF53AA37B; Tue, 18 Jul 2017 12:56:36 +0100 (IST) Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 18 Jul 2017 12:56:39 +0100 From: James Hogan To: Yongbok Kim Date: Tue, 18 Jul 2017 12:55:47 +0100 Message-ID: X-Mailer: git-send-email 2.13.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 2/14] target/mips: Fix TLBWI shadow flush for EHINV, XI, RI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Hogan , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Writing specific TLB entries with TLBWI flushes shadow TLB entries unless an existing entry is having its access permissions upgraded. This is necessary as software would from then on expect the previous mapping in that entry to no longer be in effect (even if QEMU has quietly evicted it to the shadow TLB on a TLBWR). However it won't do this if only EHINV, XI, or RI bits have been set, even if that results in a reduction of permissions, so add the necessary checks to invoke the flush when these bits are set. Fixes: 2fb58b73746e ("target-mips: add RI and XI fields to TLB entry") Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support") Signed-off-by: James Hogan Cc: Yongbok Kim Cc: Aurelien Jarno Tested-by: Yongbok Kim --- Changes in v2: - New patch. --- target/mips/op_helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e5f3ea40420e..1961cacfab18 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2029,7 +2029,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env) int idx; target_ulong VPN; uint16_t ASID; - bool G, V0, D0, V1, D1; + bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; tlb = &env->tlb->mmu.r4k.tlb[idx]; @@ -2038,17 +2038,25 @@ void r4k_helper_tlbwi(CPUMIPSState *env) VPN &= env->SEGMask; #endif ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0; G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; V0 = (env->CP0_EntryLo0 & 2) != 0; D0 = (env->CP0_EntryLo0 & 4) != 0; + XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; + RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; V1 = (env->CP0_EntryLo1 & 2) != 0; D1 = (env->CP0_EntryLo1 & 4) != 0; + XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; + RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; /* Discard cached TLB entries, unless tlbwi is just upgrading access permissions on the current entry. */ if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G || + (!tlb->EHINV && EHINV) || (tlb->V0 && !V0) || (tlb->D0 && !D0) || - (tlb->V1 && !V1) || (tlb->D1 && !D1)) { + (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1) || + (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); }