From patchwork Tue Jan 19 07:23:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 569823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D18DC1402E2 for ; Tue, 19 Jan 2016 18:25:20 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=ERKOCz/x; dkim-atps=neutral Received: from localhost ([::1]:35441 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLQfG-00030V-Dp for incoming@patchwork.ozlabs.org; Tue, 19 Jan 2016 02:25:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51980) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLQdM-0007Ta-1e for qemu-devel@nongnu.org; Tue, 19 Jan 2016 02:23:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLQdK-0008QG-VH for qemu-devel@nongnu.org; Tue, 19 Jan 2016 02:23:19 -0500 Received: from mail-pa0-x244.google.com ([2607:f8b0:400e:c03::244]:34446) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLQdK-0008Pz-MP for qemu-devel@nongnu.org; Tue, 19 Jan 2016 02:23:18 -0500 Received: by mail-pa0-x244.google.com with SMTP id yy13so33566299pab.1 for ; Mon, 18 Jan 2016 23:23:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hQa0iuGk6DqWFxMQqZq3fcuIjvyBYN02yup/zaAoO+0=; b=ERKOCz/xW5TFr4GE285pettD9McoM2IdQtOPsIimTXbruJhEknyPK9hhXbwBHK0uh3 Exs49xksYf8A1zV9ua7bdRIhn6PxOT22ah18madLUQw9m6vPXh2PnPuI+uWQV7/cFzsJ kuM8i2+K/J8d5uvAmexWWOgkiVoL1AcvP4KwdY1lFFjngi7nRsq+6Mx9QQy5IYqv6z12 TX2LhuCcUiYPleWueOffWn99SPk7ejKkusYNC+JZ26eLAhUGWvOFhF9enj/CFNK6lolG G1Dj4w3AnyxoCF2W8Jrqgjy9vvQ0Lf6AaQgfm1F/D7ep04BD1+pbB5PAKq95hRvEoiA6 eONQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hQa0iuGk6DqWFxMQqZq3fcuIjvyBYN02yup/zaAoO+0=; b=f/m36VWm5md0jkmPfTVU05FwmvPmXATanUBBVRfCMJjOSgrsVoKvdKw89TiBEFztko JUZpoHFawQnBrn0muKonxxVSENpDpOKy+Ru3g+TEqsFPq6dzq9fsrWrkGNDf/kiEKo4K iTd9M+HZQgFEf8dPRewaGR0rJ19/K7ZJ3O2w/hPK3sCDxp3we8gp8yg1IxUcxoHhF2Ri FlvONuG0xdaivGkzS1IPT+W9uTcI4aKQHRV/Hg59VVEOkIqDe9H/vyXssc/tL5kyi10o q2WZ0mRtu+v55dmWIRLDrTv1UcdgKuKywxvWaZW9jwKLv9PS7WQVED6vv86aXAaMqkHJ K59Q== X-Gm-Message-State: AG10YOT/Fboy82EUVL7yVYDQVKsUDBcJd/wQY9TOgK5gQU6EK8/+86Dx2zqyVpfENThMuQ== X-Received: by 10.66.191.34 with SMTP id gv2mr5352636pac.3.1453188198161; Mon, 18 Jan 2016 23:23:18 -0800 (PST) Received: from localhost ([2601:646:8501:c353:c839:244:eaf2:3cd]) by smtp.gmail.com with ESMTPSA id n27sm38803041pfb.53.2016.01.18.23.23.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Jan 2016 23:23:17 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.crosthwaite@xilinx.com Date: Mon, 18 Jan 2016 23:23:17 -0800 Message-Id: X-Mailer: git-send-email 2.5.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c03::244 Cc: peter.maydell@linaro.org, konstanty@ieee.org, alistair23@gmail.com Subject: [Qemu-devel] [PATCH v3 5/7] STM32F205: Connect the ADC devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Connect the ADC devices to the STM32F205 SoC. Signed-off-by: Alistair Francis --- V2: - Fix up the device/devices commit message hw/arm/stm32f205_soc.c | 22 ++++++++++++++++++++++ include/hw/arm/stm32f205_soc.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index a2bd970..28d4301 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -32,9 +32,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 0x40000800, 0x40000C00 }; static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; +static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, + 0x40012200 }; static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; +#define ADC_IRQ 18 static void stm32f205_soc_initfn(Object *obj) { @@ -55,6 +58,12 @@ static void stm32f205_soc_initfn(Object *obj) TYPE_STM32F2XX_TIMER); qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); } + + for (i = 0; i < STM_NUM_ADCS; i++) { + object_initialize(&s->adc[i], sizeof(s->adc[i]), + TYPE_STM32F2XX_ADC); + qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default()); + } } static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) @@ -128,6 +137,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_mmio_map(busdev, 0, timer_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i])); } + + /* ADC 1 to 3 */ + for (i = 0; i < STM_NUM_ADCS; i++) { + dev = DEVICE(&(s->adc[i])); + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, adc_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, ADC_IRQ)); + } } static Property stm32f205_soc_properties[] = { diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 0390eff..091e4be 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -28,6 +28,7 @@ #include "hw/misc/stm32f2xx_syscfg.h" #include "hw/timer/stm32f2xx_timer.h" #include "hw/char/stm32f2xx_usart.h" +#include "hw/adc/stm32f2xx_adc.h" #define TYPE_STM32F205_SOC "stm32f205-soc" #define STM32F205_SOC(obj) \ @@ -35,6 +36,7 @@ #define STM_NUM_USARTS 6 #define STM_NUM_TIMERS 4 +#define STM_NUM_ADCS 3 #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) @@ -52,6 +54,7 @@ typedef struct STM32F205State { STM32F2XXSyscfgState syscfg; STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; + STM32F2XXADCState adc[STM_NUM_ADCS]; } STM32F205State; #endif