From patchwork Thu Jun 28 22:38:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 936549 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=eik.bme.hu Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41GwY64rq6z9s01 for ; Fri, 29 Jun 2018 09:12:41 +1000 (AEST) Received: from localhost ([::1]:39086 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYg5d-0007hB-Vy for incoming@patchwork.ozlabs.org; Thu, 28 Jun 2018 19:12:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYg2l-0005Oe-EA for qemu-devel@nongnu.org; Thu, 28 Jun 2018 19:09:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYg2g-0005QN-Dk for qemu-devel@nongnu.org; Thu, 28 Jun 2018 19:09:39 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:59285) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fYg2g-0005Ne-6Z; Thu, 28 Jun 2018 19:09:34 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 1B9677456AF; Fri, 29 Jun 2018 01:09:33 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id F387E7456B7; Fri, 29 Jun 2018 01:09:32 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Fri, 29 Jun 2018 00:38:33 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v6 5/5] target/ppc: Relax reserved bitmask of indexed store instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The PPC440 User Manual says that if bit 31 is set, the contents of CR[CR0] are undefined for indexed store instructions but this form is not invalid. Other PPC variants confirming to recent ISA where this bit may be reserved should ignore reserved bits and not raise invalid instruction exception. In particular, MorphOS has an stwx instruction with bit 31 set and fails to boot currently because of this. With this patch it gets further. --- On sam460ex MorhpOS still has problems accessing PCI devices so cannot yet boot but does not hit the invalid instruction exception and gets further and fails due to not finding boot volume or display controller. On mac99 it actually boots but needs an OpenBIOS patch to get USB working (needed for mouse and keyboard). I'll prepare some docs on how to run different guests but for the impatient here's a little hint: -M mac99 -m 512 -vga none -device sm501 \ -prom-env 'boot-device=cd:,\mac_ppc32\boot.img' Signed-off-by: BALATON Zoltan --- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3a215a1..525d55e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6886,7 +6886,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), #define GEN_STUX(name, stop, opc2, opc3, type) \ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ -GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), +GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), #define GEN_STS(name, stop, op, type) \ GEN_ST(name, stop, op | 0x20, type) \ GEN_STU(name, stop, op | 0x21, type) \