From patchwork Fri May 29 06:31:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 477595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 80306140DED for ; Fri, 29 May 2015 16:36:12 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=vTVIQzl5; dkim-atps=neutral Received: from localhost ([::1]:33845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyDtq-0002IR-4B for incoming@patchwork.ozlabs.org; Fri, 29 May 2015 02:36:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55359) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyDtM-00020g-TJ for qemu-devel@nongnu.org; Fri, 29 May 2015 02:35:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyDtF-0004gE-Ve for qemu-devel@nongnu.org; Fri, 29 May 2015 02:35:40 -0400 Received: from mail-pa0-x22c.google.com ([2607:f8b0:400e:c03::22c]:34034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyDpk-0003wk-1T for qemu-devel@nongnu.org; Fri, 29 May 2015 02:31:56 -0400 Received: by pabru16 with SMTP id ru16so45381528pab.1 for ; Thu, 28 May 2015 23:31:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=O3OR9BVSDW0/oHiOFiFxAYPSda9U+0phAb2lqvbfeeU=; b=vTVIQzl5hKnwdwWOdgOknW7LYkcV60JHOCymTxBDDpDJIiiu95978/BKeQxeg7+/SO GlEEJRSjTYL2FNkvSJp5hTz0SQO02fNMoO6ILaTy84vpspA5wl8fkMjT6EFe3+tbP3WN mY2Nv6xXDaNE9zRkQlMMGMz948itD2KOumoPNML7Be1E36XeLdT8WA4l2e+7YZj2qFEE sVOplfVW5naDDaTXzLIoQG/g2p8/GTiCjqsnKM2w9AnUnclnDpogNdm6ffxpaS0Y0sLe dxHJZn3DsfZ7aRyhcKquXDfIoplbc3YktMvMPMIJD9TO9+7RbqW5GsXsI5YEfqQvrnAe IBOw== X-Received: by 10.68.176.131 with SMTP id ci3mr12473560pbc.146.1432881115348; Thu, 28 May 2015 23:31:55 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id zf1sm4353431pbc.43.2015.05.28.23.31.54 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 28 May 2015 23:31:54 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, edgar.iglesias@xilinx.com Date: Fri, 29 May 2015 16:31:20 +1000 Message-Id: X-Mailer: git-send-email 2.1.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22c Cc: peter.crosthwaite@xilinx.com, rth@twiddle.net, afaerber@suse.de, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v3 4/6] target-microblaze: Tidy up the base-vectors property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Rename the "xlnx.base-vectors" string to "base-vectors" and move the base_vectors variable into the cfg struct. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite --- target-microblaze/cpu-qom.h | 3 ++- target-microblaze/cpu.c | 4 ++-- target-microblaze/helper.c | 8 ++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index e08adb9..dd04199 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -56,12 +56,13 @@ typedef struct MicroBlazeCPUClass { typedef struct MicroBlazeCPU { /*< private >*/ CPUState parent_obj; - uint32_t base_vectors; + /*< public >*/ /* Microblaze Configuration Settings */ struct { bool stackprot; + uint32_t base_vectors; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index d3dad4a..0f805d3 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -120,7 +120,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); - env->sregs[SR_PC] = cpu->base_vectors; + env->sregs[SR_PC] = cpu->cfg.base_vectors; #if defined(CONFIG_USER_ONLY) env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ @@ -158,7 +158,7 @@ static const VMStateDescription vmstate_mb_cpu = { }; static Property mb_properties[] = { - DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), + DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 32896f4..69c3252 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -154,7 +154,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->base_vectors + 0x20; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; break; case EXCP_MMU: @@ -194,7 +194,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->base_vectors + 0x20; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; break; case EXCP_IRQ: @@ -235,7 +235,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] |= t; env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = cpu->base_vectors + 0x10; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -254,7 +254,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = cpu->base_vectors + 0x18; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18; } else env->sregs[SR_PC] = env->btarget; break;