From patchwork Sun May 6 19:27:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: malc X-Patchwork-Id: 157189 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D1EB5B6FAF for ; Mon, 7 May 2012 05:27:41 +1000 (EST) Received: from localhost ([::1]:56032 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SR77K-0001Fo-IY for incoming@patchwork.ozlabs.org; Sun, 06 May 2012 15:27:38 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SR77E-0001Fj-4f for qemu-devel@nongnu.org; Sun, 06 May 2012 15:27:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SR77C-00019C-5X for qemu-devel@nongnu.org; Sun, 06 May 2012 15:27:31 -0400 Received: from fe01x03-cgp.akado.ru ([77.232.31.164]:53689 helo=akado.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SR77B-000198-Ph for qemu-devel@nongnu.org; Sun, 06 May 2012 15:27:30 -0400 Received: from [10.0.66.9] ([10.0.66.9] verified) by fe01-cgp.akado.ru (CommuniGate Pro SMTP 5.2.13) with ESMTPS id 340642030; Sun, 06 May 2012 23:27:27 +0400 Date: Sun, 6 May 2012 23:27:24 +0400 (MSK) From: malc X-X-Sender: malc@linmac To: =?ISO-8859-15?Q?Andreas_F=E4rber?= In-Reply-To: <4FA6CF58.6050201@suse.de> Message-ID: References: <4FA54951.90908@suse.de> <4FA68483.8090805@suse.de> <4FA6CF58.6050201@suse.de> User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 77.232.31.164 Cc: Blue Swirl , The OpenBIOS Mailinglist , Mark Cave-Ayland , Alexander Graf , qemu-devel Subject: Re: [Qemu-devel] sparc-softmmu uninitialized memory read? X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Sun, 6 May 2012, Andreas F?rber wrote: > Am 06.05.2012 18:44, schrieb Blue Swirl: > > On Sun, May 6, 2012 at 2:02 PM, Andreas F?rber wrote: > >> Am 06.05.2012 13:32, schrieb Blue Swirl: > >>> On Sat, May 5, 2012 at 3:37 PM, Andreas F?rber wrote: > >>>> Hello Blue, [..snip..] > Great! I have tested the following workaround: > > diff --git a/hw/sun4m.c b/hw/sun4m.c > index 34088ad..55d5bdc 100644 > --- a/hw/sun4m.c > +++ b/hw/sun4m.c > @@ -755,6 +755,7 @@ static int ram_init1(SysBusDevice *dev) > RamDevice *d = FROM_SYSBUS(RamDevice, dev); > > memory_region_init_ram(&d->ram, "sun4m.ram", d->size); > + memset(memory_region_get_ram_ptr(&d->ram), 0, d->size); > vmstate_register_ram_global(&d->ram); > sysbus_init_mmio(dev, &d->ram); > return 0; > > This makes sparc32 work on ppc with malc's attached patch (and doesn't > break on x86_64). > The attached patch is broken for non SysV calling conventions, would be nice if you could test things on Darwin (and, if your power5 box still has AIX, on AIX) diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index dc40716..311af18 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -509,7 +509,7 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg) #include "../../softmmu_defs.h" #ifdef CONFIG_TCG_PASS_AREG0 -#error CONFIG_TCG_PASS_AREG0 is not supported +/* #error CONFIG_TCG_PASS_AREG0 is not supported */ /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, int mmu_idx) */ static const void * const qemu_ld_helpers[4] = { @@ -614,6 +614,24 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) #endif /* slow path */ +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0); +#if TARGET_LONG_BITS == 32 + tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg); + tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index); +#else + { +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + int ir = 5; +#else + int ir = 4; +#endif + tcg_out_mov (s, TCG_TYPE_I32, ir, addr_reg2); + tcg_out_mov (s, TCG_TYPE_I32, ir + 1, addr_reg); + tcg_out_movi (s, TCG_TYPE_I32, ir + 2, mem_index); + } +#endif +#else #if TARGET_LONG_BITS == 32 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg); tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index); @@ -622,6 +640,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg); tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index); #endif +#endif tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1); switch (opc) { @@ -810,6 +829,17 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) #endif /* slow path */ +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0); +#if TARGET_LONG_BITS == 32 + tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg); + ir = 5; +#else + tcg_out_mov (s, TCG_TYPE_I32, 5, addr_reg2); + tcg_out_mov (s, TCG_TYPE_I32, 6, addr_reg); + ir = 7; +#endif +#else #if TARGET_LONG_BITS == 32 tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg); ir = 4; @@ -822,6 +852,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) ir = 4; #endif #endif +#endif switch (opc) { case 0: @@ -844,7 +875,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg); break; case 3: -#ifdef TCG_TARGET_CALL_ALIGN_ARGS +#if defined TCG_TARGET_CALL_ALIGN_ARGS && !defined CONFIG_TCG_PASS_AREG0 ir = 5; #endif tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2);