diff mbox

target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors

Message ID alpine.DEB.1.10.1411201116250.2881@tp.orcam.me.uk
State New
Headers show

Commit Message

Maciej W. Rozycki Dec. 20, 2014, 11 p.m. UTC 
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
Hi,

 As we discussed previously, please apply.

 [This got stuck in postponed e-mail, I thought I had sent it already.]

  Maciej

qemu-mips-5kc-cu1.diff
diff mbox

Patch

Index: qemu-git-trunk/target-mips/translate_init.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate_init.c	2014-11-20 10:47:31.578938672 +0000
+++ qemu-git-trunk/target-mips/translate_init.c	2014-11-20 10:47:39.078939989 +0000
@@ -474,7 +474,7 @@  static const mips_def_t mips_defs[] =
         .CP0_LLAddr_shift = 4,
         .SYNCI_Step = 32,
         .CCRes = 2,
-        .CP0_Status_rw_bitmask = 0x32F8FFFF,
+        .CP0_Status_rw_bitmask = 0x12F8FFFF,
         .SEGBITS = 42,
         .PABITS = 36,
         .insn_flags = CPU_MIPS64,
@@ -575,7 +575,7 @@  static const mips_def_t mips_defs[] =
         .CP0_LLAddr_shift = 4,
         .SYNCI_Step = 32,
         .CCRes = 2,
-        .CP0_Status_rw_bitmask = 0x32F8FFFF,
+        .CP0_Status_rw_bitmask = 0x12F8FFFF,
         .SEGBITS = 42,
         .PABITS = 36,
         .insn_flags = CPU_MIPS64R2,