From patchwork Wed Nov 12 15:21:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 410007 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3D1811400AB for ; Thu, 13 Nov 2014 02:23:37 +1100 (AEDT) Received: from localhost ([::1]:55281 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XoZlf-0005Cs-3T for incoming@patchwork.ozlabs.org; Wed, 12 Nov 2014 10:23:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XoZlG-0004rM-Ur for qemu-devel@nongnu.org; Wed, 12 Nov 2014 10:23:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XoZlA-000847-48 for qemu-devel@nongnu.org; Wed, 12 Nov 2014 10:23:10 -0500 Received: from relay1.mentorg.com ([192.94.38.131]:41469) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XoZl9-0007aA-V2 for qemu-devel@nongnu.org; Wed, 12 Nov 2014 10:23:04 -0500 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=SVR-IES-FEM-01.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1XoZk6-0004jE-Jo from Maciej_Rozycki@mentor.com ; Wed, 12 Nov 2014 07:21:58 -0800 Received: from localhost (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server (TLS) id 14.3.181.6; Wed, 12 Nov 2014 15:21:56 +0000 Date: Wed, 12 Nov 2014 15:21:53 +0000 From: "Maciej W. Rozycki" To: Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 192.94.38.131 Cc: Leon Alrae , Aurelien Jarno Subject: [Qemu-devel] [PATCH] mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by using register addition operations. This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying `rs' to `rd' verbatim. This is not the case with OPC_ADDIU where a sign-extension from bit #31 is made, unless in the uninteresting case of `rs' being 0, losing the upper 32 bits of the value copied for any proper 64-bit values. This also serves as an optimization as one op is produced in generated code rather than two (again, unless `rs' is 0, where it doesn't change anything). Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae --- This is rather obvious, but I also pushed it through full bare-iron GCC regression testing with an o32 big-endian microMIPS multilib. That includes several instances of both instructions. No changes in results were observed with the patch applied compared to the original version. I wonder if all these move operations shouldn't actually be switched to using OPC_OR that is agnostic to the machine word size regardless of the operand selection. But that is something to consider separately. So meanwhile, please apply. Maciej qemu-umips-move.diff Index: qemu-git-trunk/target-mips/translate.c =================================================================== --- qemu-git-trunk.orig/target-mips/translate.c 2014-11-02 17:57:16.998924336 +0000 +++ qemu-git-trunk/target-mips/translate.c 2014-11-02 17:57:19.498930155 +0000 @@ -13492,8 +13492,8 @@ static int decode_micromips_opc (CPUMIPS rs = rs_rt_enc[enc_rs]; rt = rs_rt_enc[enc_rt]; - gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0); - gen_arith_imm(ctx, OPC_ADDIU, re, rt, 0); + gen_arith(ctx, OPC_ADDU, rd, rs, 0); + gen_arith(ctx, OPC_ADDU, re, rt, 0); } break; case LBU16: @@ -13574,7 +13574,7 @@ static int decode_micromips_opc (CPUMIPS int rd = uMIPS_RD5(ctx->opcode); int rs = uMIPS_RS5(ctx->opcode); - gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0); + gen_arith(ctx, OPC_ADDU, rd, rs, 0); } break; case ANDI16: