From patchwork Thu Dec 17 23:47:54 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 41477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2D5F9B6F18 for ; Sun, 20 Dec 2009 08:29:49 +1100 (EST) Received: from localhost ([127.0.0.1]:55964 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NM6ry-0001SK-83 for incoming@patchwork.ozlabs.org; Sat, 19 Dec 2009 16:29:46 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NM6iN-0006fc-45 for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:51 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NM6iJ-0006dJ-Vg for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:48 -0500 Received: from [199.232.76.173] (port=49344 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NM6iJ-0006dB-JJ for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:47 -0500 Received: from are.twiddle.net ([75.149.56.221]:45158) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NM6iI-0000g1-Lz for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:47 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id 1BA73A32; Sat, 19 Dec 2009 13:19:45 -0800 (PST) Message-Id: In-Reply-To: References: From: Richard Henderson Date: Thu, 17 Dec 2009 15:47:54 -0800 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 3/6] tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The test TCG_TARGET_REG_BITS==64 is exactly the feature that we are checking for, whereas something involving __sparc_v9__ or __sparc_v8plus__ should be reserved for something ISA related, as with SMULX. --- tcg/sparc/tcg-target.c | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 78b26c9..78f851d 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -348,13 +348,13 @@ static inline void tcg_out_ld_ptr(TCGContext *s, int ret, { if (!check_fit_tl(arg, 10)) tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL); -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) - tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | - INSN_IMM13(arg & 0x3ff)); -#else - tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | - INSN_IMM13(arg & 0x3ff)); -#endif + if (TCG_TARGET_REG_BITS == 64) { + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | + INSN_IMM13(arg & 0x3ff)); + } else { + tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | + INSN_IMM13(arg & 0x3ff)); + } } static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) @@ -447,7 +447,7 @@ static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index) } } -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index) { int32_t val; @@ -493,7 +493,7 @@ static void tcg_out_brcond_i32(TCGContext *s, int cond, tcg_out_nop(s); } -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 static void tcg_out_brcond_i64(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, int const_arg2, int label_index) @@ -989,7 +989,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); break; -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 #define OP_32_64(x) \ glue(glue(case INDEX_op_, x), _i32:) \ glue(glue(case INDEX_op_, x), _i64:) @@ -1010,7 +1010,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, tcg_out_ldst(s, args[0], args[1], args[2], LDSH); break; case INDEX_op_ld_i32: -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 case INDEX_op_ld32u_i64: #endif tcg_out_ldst(s, args[0], args[1], args[2], LDUW); @@ -1022,7 +1022,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, tcg_out_ldst(s, args[0], args[1], args[2], STH); break; case INDEX_op_st_i32: -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 case INDEX_op_st32_i64: #endif tcg_out_ldst(s, args[0], args[1], args[2], STW); @@ -1106,7 +1106,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, tcg_out_qemu_st(s, args, 2); break; -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 case INDEX_op_movi_i64: tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); break; @@ -1208,7 +1208,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_qemu_st16, { "L", "L" } }, { INDEX_op_qemu_st32, { "L", "L" } }, -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 { INDEX_op_mov_i64, { "r", "r" } }, { INDEX_op_movi_i64, { "r" } }, { INDEX_op_ld8u_i64, { "r", "r" } }, @@ -1246,7 +1246,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { void tcg_target_init(TCGContext *s) { tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); #endif tcg_regset_set32(tcg_target_call_clobber_regs, 0, @@ -1267,7 +1267,7 @@ void tcg_target_init(TCGContext *s) tcg_regset_clear(s->reserved_regs); tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) +#if TCG_TARGET_REG_BITS == 64 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use #endif tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use