From patchwork Fri Oct 23 01:31:29 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: TeLeMan X-Patchwork-Id: 36757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 059BDB7BC7 for ; Fri, 23 Oct 2009 12:32:25 +1100 (EST) Received: from localhost ([127.0.0.1]:35535 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N190q-0004c8-6S for incoming@patchwork.ozlabs.org; Thu, 22 Oct 2009 21:32:16 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N190D-0004aL-Oq for qemu-devel@nongnu.org; Thu, 22 Oct 2009 21:31:37 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N1909-0004V0-7D for qemu-devel@nongnu.org; Thu, 22 Oct 2009 21:31:37 -0400 Received: from [199.232.76.173] (port=44109 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N1908-0004Ud-UT for qemu-devel@nongnu.org; Thu, 22 Oct 2009 21:31:33 -0400 Received: from mail-px0-f179.google.com ([209.85.216.179]:49314) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N1907-0004Gt-RL for qemu-devel@nongnu.org; Thu, 22 Oct 2009 21:31:32 -0400 Received: by pxi9 with SMTP id 9so354611pxi.4 for ; Thu, 22 Oct 2009 18:31:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=rZewWcovqwcJ6TiDgc9xY24u46RVv3DPaPtm6VPekRY=; b=To5SrjI0QgeXh4JKCw7gPoMi/lq6qiNS6b3vODuEDNQKb5rri8E7W3i+1stADrBLBX PSNUNUhuCnZT6RdnId/jdNEyRP260tLSIQDp813ZMGQPUylv6hBP+FbnMQUohig8BjpB jqPGa2jgT+oFTU32g7DX0glZibL2mLmCp9TI8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=ttwMpNpQ+XCcGKltA6NtE6U2BNvNI6eQ+yVDWA97B8MxhrBQIxOeiHN6WG2XIw6zJd R9d+vXf6vTNM/kabZ1SHt+C1qW9TWi0Gole3ga6RDxEbsCDxwSqoRoSmF54WxBe9Lo+L +nvDY/6andzXAsUfDQP17AP6paUufcWFSqBtI= MIME-Version: 1.0 Received: by 10.140.163.7 with SMTP id l7mr1790742rve.166.1256261489418; Thu, 22 Oct 2009 18:31:29 -0700 (PDT) Date: Fri, 23 Oct 2009 09:31:29 +0800 Message-ID: From: TeLeMan To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] Re: [PATCH] tcg, tci: Add TCG and interpreter for bytecode (virtual machine) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Tested i386-softmmu only. Now tci can run windows xp sp2 and its speed is about 6 times slower than jit. --- SUN OF A BEACH Subject: [PATCH 1/5] tci: fix op_sar_iXX and op_ext16s_iXX --- tcg/tci.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e467b3a..81c415c 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -206,7 +206,7 @@ static uint16_t tci_read_r16(uint8_t **tb_ptr) } /* Read indexed register (16 bit signed) from bytecode. */ -static uint16_t tci_read_r16s(uint8_t **tb_ptr) +static int16_t tci_read_r16s(uint8_t **tb_ptr) { uint16_t value = tci_read_reg16s(**tb_ptr); *tb_ptr += 1; @@ -549,7 +549,7 @@ unsigned long tcg_qemu_tb_exec(uint8_t *tb_ptr) t0 = *tb_ptr++; t1 = tci_read_ri32(&tb_ptr); t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (t1 >> t2) | (t1 & (1UL << 31))); + tci_write_reg32(t0, ((int32_t)t1 >> t2)); break; #ifdef TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: @@ -794,7 +794,7 @@ unsigned long tcg_qemu_tb_exec(uint8_t *tb_ptr) t0 = *tb_ptr++; t1 = tci_read_ri64(&tb_ptr); t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, (t1 >> t2) | (t1 & (1ULL << 63))); + tci_write_reg64(t0, ((int64_t)t1 >> t2)); break; #ifdef TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: