[v2,5/7] target-arm: Remove old code and replace with new functions

Remove the old PMCCNTR code and replace it with calls to the new
pmccntr_sync() function and the CCNT_ENABLED macro

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---

 target-arm/helper.c |   27 ++++-----------------------
 1 files changed, 4 insertions(+), 23 deletions(-)

On Thu, Jun 26, 2014 at 3:02 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Remove the old PMCCNTR code and replace it with calls to the new
> pmccntr_sync() function and the CCNT_ENABLED macro

arm_ccnt_enabled() function.

>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
>  target-arm/helper.c |   27 ++++-----------------------
>  1 files changed, 4 insertions(+), 23 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 016fe47..0bd00cb 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -609,20 +609,7 @@ void pmccntr_sync(CPUARMState *env)
>  static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                         uint64_t value)
>  {
> -    uint64_t temp_ticks;
> -
> -    temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
> -                          get_ticks_per_sec(), 1000000);
> -
> -    if (env->cp15.c9_pmcr & PMCRE) {
> -        /* If the counter is enabled */
> -        if (env->cp15.c9_pmcr & PMCRD) {
> -            /* Increment once every 64 processor clock cycles */
> -            env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
> -        } else {
> -            env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
> -        }
> -    }
> +    pmccntr_sync(env);
>
>      if (value & PMCRC) {
>          /* The counter has been reset */
> @@ -633,20 +620,14 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>      env->cp15.c9_pmcr &= ~0x39;
>      env->cp15.c9_pmcr |= (value & 0x39);
>
> -    if (env->cp15.c9_pmcr & PMCRE) {
> -        if (env->cp15.c9_pmcr & PMCRD) {
> -            /* Increment once every 64 processor clock cycles */
> -            temp_ticks /= 64;
> -        }
> -        env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
> -    }
> +    pmccntr_sync(env);
>  }
>
>  static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
>  {
>      uint64_t total_ticks;
>
> -    if (!(env->cp15.c9_pmcr & PMCRE)) {
> +    if (!arm_ccnt_enabled(env)) {
>          /* Counter is disabled, do not change value */
>          return env->cp15.c15_ccnt;
>      }
> @@ -666,7 +647,7 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>  {
>      uint64_t total_ticks;
>
> -    if (!(env->cp15.c9_pmcr & PMCRE)) {
> +    if (!arm_ccnt_enabled(env)) {

Is it valid to write to the running counter?

If so you can sync(), update sync() to implement easily now and drop the if.

Regards,
Peter

>          /* Counter is disabled, set the absolute value */
>          env->cp15.c15_ccnt = value;
>          return;
> --
> 1.7.1
>
>

On Thu, Jun 26, 2014 at 9:38 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Thu, Jun 26, 2014 at 3:02 PM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> Remove the old PMCCNTR code and replace it with calls to the new
>> pmccntr_sync() function and the CCNT_ENABLED macro
>
> arm_ccnt_enabled() function.
>
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>>
>>  target-arm/helper.c |   27 ++++-----------------------
>>  1 files changed, 4 insertions(+), 23 deletions(-)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 016fe47..0bd00cb 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -609,20 +609,7 @@ void pmccntr_sync(CPUARMState *env)
>>  static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>>                         uint64_t value)
>>  {
>> -    uint64_t temp_ticks;
>> -
>> -    temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
>> -                          get_ticks_per_sec(), 1000000);
>> -
>> -    if (env->cp15.c9_pmcr & PMCRE) {
>> -        /* If the counter is enabled */
>> -        if (env->cp15.c9_pmcr & PMCRD) {
>> -            /* Increment once every 64 processor clock cycles */
>> -            env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
>> -        } else {
>> -            env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
>> -        }
>> -    }
>> +    pmccntr_sync(env);
>>
>>      if (value & PMCRC) {
>>          /* The counter has been reset */
>> @@ -633,20 +620,14 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>>      env->cp15.c9_pmcr &= ~0x39;
>>      env->cp15.c9_pmcr |= (value & 0x39);
>>
>> -    if (env->cp15.c9_pmcr & PMCRE) {
>> -        if (env->cp15.c9_pmcr & PMCRD) {
>> -            /* Increment once every 64 processor clock cycles */
>> -            temp_ticks /= 64;
>> -        }
>> -        env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
>> -    }
>> +    pmccntr_sync(env);
>>  }
>>
>>  static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
>>  {
>>      uint64_t total_ticks;
>>
>> -    if (!(env->cp15.c9_pmcr & PMCRE)) {
>> +    if (!arm_ccnt_enabled(env)) {
>>          /* Counter is disabled, do not change value */
>>          return env->cp15.c15_ccnt;
>>      }
>> @@ -666,7 +647,7 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>>  {
>>      uint64_t total_ticks;
>>
>> -    if (!(env->cp15.c9_pmcr & PMCRE)) {
>> +    if (!arm_ccnt_enabled(env)) {
>
> Is it valid to write to the running counter?

It is a RW register, so I'm assuming it can be set

>
> If so you can sync(), update sync() to implement easily now and drop the if.

It's not the same process as the other syncs. This logic includes the value that
is being written, which the sync function doesn't. It would require
changes to the
sync function, with values to be passed in. It doesn't seem like it's
worth doing

>
> Regards,
> Peter
>
>>          /* Counter is disabled, set the absolute value */
>>          env->cp15.c15_ccnt = value;
>>          return;
>> --
>> 1.7.1
>>
>>
>