| Message ID | PSXP216MB027793B449E7DAAB995E0F33DD390@PSXP216MB0277.KORP216.PROD.OUTLOOK.COM |
|---|---|
| State | New |
| Headers | show |
| Series | Add the STM32F405 and Netduino Plus 2 machine | expand |
Hi Alistair, Le 4/29/19 à 7:33 AM, Alistair Francis a écrit : > Signed-off-by: Alistair Francis <alistair@alistair23.me> > --- > MAINTAINERS | 8 + > default-configs/arm-softmmu.mak | 1 + > hw/arm/Kconfig | 3 + > hw/arm/Makefile.objs | 1 + > hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ > include/hw/arm/stm32f405_soc.h | 70 ++++++++ > 6 files changed, 375 insertions(+) > create mode 100644 hw/arm/stm32f405_soc.c > create mode 100644 include/hw/arm/stm32f405_soc.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index dabbfccf9c..c9772735cf 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -803,6 +803,14 @@ F: hw/adc/* > F: hw/ssi/stm32f2xx_spi.c > F: include/hw/*/stm32*.h > > +STM32F405 > +M: Alistair Francis <alistair@alistair23.me> > +M: Peter Maydell <peter.maydell@linaro.org> > +S: Maintained > +F: hw/arm/stm32f405_soc.c > +F: hw/misc/stm32f4xx_syscfg.c > +F: hw/misc/stm32f4xx_exti.c > + > Netduino 2 > M: Alistair Francis <alistair@alistair23.me> > M: Peter Maydell <peter.maydell@linaro.org> > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > index 8eb57de211..e079f10624 100644 > --- a/default-configs/arm-softmmu.mak > +++ b/default-configs/arm-softmmu.mak > @@ -98,6 +98,7 @@ CONFIG_STM32F2XX_SPI=y > CONFIG_STM32F205_SOC=y > CONFIG_STM32F4XX_SYSCFG=y > CONFIG_STM32F4XX_EXTI=y > +CONFIG_STM32F405_SOC=y Why not using 4xx instead of 405 in this patch as well? > CONFIG_NRF51_SOC=y > > CONFIG_CMSDK_APB_TIMER=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index d298fbdc89..3a98bce15a 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -62,6 +62,9 @@ config RASPI > config STM32F205_SOC > bool > > +config STM32F405_SOC > + bool > + > config XLNX_ZYNQMP_ARM > bool > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index fa57c7c770..36c3ff54c3 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -26,6 +26,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o > obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o > obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o > obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o > +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o > obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o > obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o > obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o > diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c > new file mode 100644 > index 0000000000..83adec51a2 > --- /dev/null > +++ b/hw/arm/stm32f405_soc.c > @@ -0,0 +1,292 @@ > +/* > + * STM32F405 SoC > + * > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu-common.h" > +#include "hw/arm/arm.h" > +#include "exec/address-spaces.h" > +#include "hw/arm/stm32f405_soc.h" > +#include "hw/misc/unimp.h" > + > +#define SYSCFG_ADD 0x40013800 > +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, > + 0x40004C00, 0x40005000, 0x40011400, > + 0x40007800, 0x40007C00 }; > +/* At the moment only Timer 2 to 5 are modelled */ > +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, > + 0x40000800, 0x40000C00 }; > +#define ADC_ADDR 0x40012000 > +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, > + 0x40013400, 0x40015000, 0x40015400 }; > +#define EXTI_ADDR 0x40013C00 > + > +#define SYSCFG_IRQ 71 > +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; > +static const int timer_irq[] = { 28, 29, 30, 50 }; > +#define ADC_IRQ 18 > +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; > +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, > + 40, 40, 40, 40, 40} ; > + > + > +static void stm32f405_soc_initfn(Object *obj) > +{ > + STM32F405State *s = STM32F405_SOC(obj); > + int i; > + > + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), > + TYPE_ARMV7M); > + > + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), > + TYPE_STM32F4XX_SYSCFG); > + > + for (i = 0; i < STM_NUM_USARTS; i++) { > + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], > + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); > + } > + > + for (i = 0; i < STM_NUM_TIMERS; i++) { > + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], > + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); > + } > + > + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); > + > + for (i = 0; i < STM_NUM_ADCS; i++) { > + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), > + TYPE_STM32F2XX_ADC); > + } > + > + for (i = 0; i < STM_NUM_SPIS; i++) { > + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), > + TYPE_STM32F2XX_SPI); > + } > + > + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), > + TYPE_STM32F4XX_EXTI); > +} > + > +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > +{ > + STM32F405State *s = STM32F405_SOC(dev_soc); > + DeviceState *dev, *armv7m; > + SysBusDevice *busdev; > + Error *err = NULL; > + int i; > + > + MemoryRegion *system_memory = get_system_memory(); > + MemoryRegion *sram = g_new(MemoryRegion, 1); > + MemoryRegion *flash = g_new(MemoryRegion, 1); > + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); > + > + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, > + &error_fatal); > + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", > + flash, 0, FLASH_SIZE); > + > + memory_region_set_readonly(flash, true); > + memory_region_set_readonly(flash_alias, true); > + > + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); > + memory_region_add_subregion(system_memory, 0, flash_alias); > + > + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, > + &error_fatal); > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > + > + armv7m = DEVICE(&s->armv7m); > + qdev_prop_set_uint32(armv7m, "num-irq", 96); > + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), > + "memory", &error_abort); > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + > + /* System configuration controller */ > + dev = DEVICE(&s->syscfg); > + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); > + > + /* Attach UART (uses USART registers) and USART controllers */ > + for (i = 0; i < STM_NUM_USARTS; i++) { > + dev = DEVICE(&(s->usart[i])); > + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); > + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, usart_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); > + } > + > + /* Timer 2 to 5 */ > + for (i = 0; i < STM_NUM_TIMERS; i++) { > + dev = DEVICE(&(s->timer[i])); > + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); > + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, timer_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); > + } > + > + /* ADC device, the IRQs are ORed together */ > + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, > + "num-lines", &err); > + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, > + qdev_get_gpio_in(armv7m, ADC_IRQ)); > + > + dev = DEVICE(&(s->adc[i])); > + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, ADC_ADDR); > + sysbus_connect_irq(busdev, 0, > + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); > + > + /* SPI devices */ > + for (i = 0; i < STM_NUM_SPIS; i++) { > + dev = DEVICE(&(s->spi[i])); > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, spi_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); > + } > + > + /* EXTI device */ > + dev = DEVICE(&s->exti); > + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, EXTI_ADDR); > + for (i = 0; i < 16; i++) { > + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); > + } > + for (i = 0; i < 16; i++) { > + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); > + } > + > + create_unimplemented_device("timer[6]", 0x40001000, 0x400 - 1); > + create_unimplemented_device("timer[7]", 0x40001400, 0x400 - 1); > + create_unimplemented_device("timer[12]", 0x40001800, 0x400 - 1); > + create_unimplemented_device("timer[13]", 0x40001C00, 0x400 - 1); > + create_unimplemented_device("timer[14]", 0x40002000, 0x400 - 1); > + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400 - 1); > + create_unimplemented_device("WWDG", 0x40002C00, 0x400 - 1); > + create_unimplemented_device("IWDG", 0x40003000, 0x400 - 1); > + create_unimplemented_device("I2S2ext", 0x40003000, 0x400 - 1); > + create_unimplemented_device("I2S3ext", 0x40004000, 0x400 - 1); > + create_unimplemented_device("I2C1", 0x40005400, 0x400 - 1); > + create_unimplemented_device("I2C2", 0x40005800, 0x400 - 1); > + create_unimplemented_device("I2C3", 0x40005C00, 0x400 - 1); > + create_unimplemented_device("CAN1", 0x40006400, 0x400 - 1); > + create_unimplemented_device("CAN2", 0x40006800, 0x400 - 1); > + create_unimplemented_device("PWR", 0x40007000, 0x400 - 1); > + create_unimplemented_device("DAC", 0x40007400, 0x400 - 1); > + create_unimplemented_device("timer[1]", 0x40010000, 0x400 - 1); > + create_unimplemented_device("timer[8]", 0x40010400, 0x400 - 1); > + create_unimplemented_device("SDIO", 0x40012C00, 0x400 - 1); > + create_unimplemented_device("timer[9]", 0x40014000, 0x400 - 1); > + create_unimplemented_device("timer[10]", 0x40014400, 0x400 - 1); > + create_unimplemented_device("timer[11]", 0x40014800, 0x400 - 1); > + create_unimplemented_device("GPIOA", 0x40020000, 0x400 - 1); > + create_unimplemented_device("GPIOB", 0x40020400, 0x400 - 1); > + create_unimplemented_device("GPIOC", 0x40020800, 0x400 - 1); > + create_unimplemented_device("GPIOD", 0x40020C00, 0x400 - 1); > + create_unimplemented_device("GPIOE", 0x40021000, 0x400 - 1); > + create_unimplemented_device("GPIOF", 0x40021400, 0x400 - 1); > + create_unimplemented_device("GPIOG", 0x40021800, 0x400 - 1); > + create_unimplemented_device("GPIOH", 0x40021C00, 0x400 - 1); > + create_unimplemented_device("GPIOI", 0x40022000, 0x400 - 1); > + create_unimplemented_device("CRC", 0x40023000, 0x400 - 1); > + create_unimplemented_device("RCC", 0x40023800, 0x400 - 1); > + create_unimplemented_device("Flash Int", 0x40023C00, 0x400 - 1); > + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400 - 1); > + create_unimplemented_device("DMA1", 0x40026000, 0x400 - 1); > + create_unimplemented_device("DMA2", 0x40026400, 0x400 - 1); > + create_unimplemented_device("Ethernet", 0x40028000, 0x1400 - 1); > + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000 - 1); > + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000 - 1); > + create_unimplemented_device("DCMI", 0x50050000, 0x400 - 1); > + create_unimplemented_device("RNG", 0x50060800, 0x400 - 1); > +} > + > +static Property stm32f405_soc_properties[] = { > + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = stm32f405_soc_realize; > + dc->props = stm32f405_soc_properties; > +} > + > +static const TypeInfo stm32f405_soc_info = { > + .name = TYPE_STM32F405_SOC, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(STM32F405State), > + .instance_init = stm32f405_soc_initfn, > + .class_init = stm32f405_soc_class_init, > +}; > + > +static void stm32f405_soc_types(void) > +{ > + type_register_static(&stm32f405_soc_info); > +} > + > +type_init(stm32f405_soc_types) > diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h > new file mode 100644 > index 0000000000..f0aec53d32 > --- /dev/null > +++ b/include/hw/arm/stm32f405_soc.h > @@ -0,0 +1,70 @@ > +/* > + * STM32F405 SoC > + * > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_ARM_STM32F405_SOC_H > +#define HW_ARM_STM32F405_SOC_H > + > +#include "hw/misc/stm32f4xx_syscfg.h" > +#include "hw/timer/stm32f2xx_timer.h" > +#include "hw/char/stm32f2xx_usart.h" > +#include "hw/adc/stm32f2xx_adc.h" > +#include "hw/misc/stm32f4xx_exti.h" > +#include "hw/or-irq.h" > +#include "hw/ssi/stm32f2xx_spi.h" > +#include "hw/arm/armv7m.h" > + > +#define TYPE_STM32F405_SOC "stm32f405-soc" > +#define STM32F405_SOC(obj) \ > + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) > + > +#define STM_NUM_USARTS 7 > +#define STM_NUM_TIMERS 4 > +#define STM_NUM_ADCS 6 > +#define STM_NUM_SPIS 6 > + > +#define FLASH_BASE_ADDRESS 0x08000000 > +#define FLASH_SIZE (1024 * 1024) > +#define SRAM_BASE_ADDRESS 0x20000000 > +#define SRAM_SIZE (192 * 1024) > + > +typedef struct STM32F405State { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + char *cpu_type; > + > + ARMv7MState armv7m; > + > + STM32F4xxSyscfgState syscfg; > + STM32F4xxExtiState exti; > + STM32F2XXUsartState usart[STM_NUM_USARTS]; > + STM32F2XXTimerState timer[STM_NUM_TIMERS]; > + STM32F2XXADCState adc[STM_NUM_ADCS]; > + STM32F2XXSPIState spi[STM_NUM_SPIS]; > + > + qemu_or_irq *adc_irqs; > +} STM32F405State; > + > +#endif >
On 4/29/19 7:33 AM, Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair@alistair23.me> > --- > MAINTAINERS | 8 + > default-configs/arm-softmmu.mak | 1 + > hw/arm/Kconfig | 3 + > hw/arm/Makefile.objs | 1 + > hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ > include/hw/arm/stm32f405_soc.h | 70 ++++++++ > 6 files changed, 375 insertions(+) > create mode 100644 hw/arm/stm32f405_soc.c > create mode 100644 include/hw/arm/stm32f405_soc.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index dabbfccf9c..c9772735cf 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -803,6 +803,14 @@ F: hw/adc/* > F: hw/ssi/stm32f2xx_spi.c > F: include/hw/*/stm32*.h > > +STM32F405 > +M: Alistair Francis <alistair@alistair23.me> > +M: Peter Maydell <peter.maydell@linaro.org> > +S: Maintained > +F: hw/arm/stm32f405_soc.c > +F: hw/misc/stm32f4xx_syscfg.c > +F: hw/misc/stm32f4xx_exti.c > + > Netduino 2 > M: Alistair Francis <alistair@alistair23.me> > M: Peter Maydell <peter.maydell@linaro.org> > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > index 8eb57de211..e079f10624 100644 > --- a/default-configs/arm-softmmu.mak > +++ b/default-configs/arm-softmmu.mak > @@ -98,6 +98,7 @@ CONFIG_STM32F2XX_SPI=y > CONFIG_STM32F205_SOC=y > CONFIG_STM32F4XX_SYSCFG=y > CONFIG_STM32F4XX_EXTI=y > +CONFIG_STM32F405_SOC=y > CONFIG_NRF51_SOC=y > > CONFIG_CMSDK_APB_TIMER=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index d298fbdc89..3a98bce15a 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -62,6 +62,9 @@ config RASPI > config STM32F205_SOC > bool > > +config STM32F405_SOC > + bool > + > config XLNX_ZYNQMP_ARM > bool > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index fa57c7c770..36c3ff54c3 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -26,6 +26,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o > obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o > obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o > obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o > +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o > obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o > obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o > obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o > diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c > new file mode 100644 > index 0000000000..83adec51a2 > --- /dev/null > +++ b/hw/arm/stm32f405_soc.c > @@ -0,0 +1,292 @@ > +/* > + * STM32F405 SoC > + * > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 2019? > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu-common.h" > +#include "hw/arm/arm.h" > +#include "exec/address-spaces.h" > +#include "hw/arm/stm32f405_soc.h" > +#include "hw/misc/unimp.h" > + > +#define SYSCFG_ADD 0x40013800 > +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, > + 0x40004C00, 0x40005000, 0x40011400, > + 0x40007800, 0x40007C00 }; > +/* At the moment only Timer 2 to 5 are modelled */ > +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, > + 0x40000800, 0x40000C00 }; > +#define ADC_ADDR 0x40012000 > +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, > + 0x40013400, 0x40015000, 0x40015400 }; > +#define EXTI_ADDR 0x40013C00 > + > +#define SYSCFG_IRQ 71 > +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; > +static const int timer_irq[] = { 28, 29, 30, 50 }; > +#define ADC_IRQ 18 > +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; > +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, > + 40, 40, 40, 40, 40} ; > + > + > +static void stm32f405_soc_initfn(Object *obj) > +{ > + STM32F405State *s = STM32F405_SOC(obj); > + int i; > + > + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), > + TYPE_ARMV7M); > + > + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), > + TYPE_STM32F4XX_SYSCFG); > + > + for (i = 0; i < STM_NUM_USARTS; i++) { > + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], > + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); > + } > + > + for (i = 0; i < STM_NUM_TIMERS; i++) { > + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], > + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); > + } > + > + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); > + > + for (i = 0; i < STM_NUM_ADCS; i++) { > + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), > + TYPE_STM32F2XX_ADC); > + } > + > + for (i = 0; i < STM_NUM_SPIS; i++) { > + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), > + TYPE_STM32F2XX_SPI); > + } > + > + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), > + TYPE_STM32F4XX_EXTI); > +} > + > +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > +{ > + STM32F405State *s = STM32F405_SOC(dev_soc); > + DeviceState *dev, *armv7m; > + SysBusDevice *busdev; > + Error *err = NULL; > + int i; > + > + MemoryRegion *system_memory = get_system_memory(); > + MemoryRegion *sram = g_new(MemoryRegion, 1); > + MemoryRegion *flash = g_new(MemoryRegion, 1); > + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); > + > + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, > + &error_fatal); > + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", > + flash, 0, FLASH_SIZE); > + > + memory_region_set_readonly(flash, true); > + memory_region_set_readonly(flash_alias, true); > + > + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); > + memory_region_add_subregion(system_memory, 0, flash_alias); > + > + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, > + &error_fatal); > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > + > + armv7m = DEVICE(&s->armv7m); > + qdev_prop_set_uint32(armv7m, "num-irq", 96); > + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), > + "memory", &error_abort); > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + > + /* System configuration controller */ > + dev = DEVICE(&s->syscfg); > + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); > + > + /* Attach UART (uses USART registers) and USART controllers */ > + for (i = 0; i < STM_NUM_USARTS; i++) { > + dev = DEVICE(&(s->usart[i])); > + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); > + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, usart_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); > + } > + > + /* Timer 2 to 5 */ > + for (i = 0; i < STM_NUM_TIMERS; i++) { > + dev = DEVICE(&(s->timer[i])); > + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); > + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, timer_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); > + } > + > + /* ADC device, the IRQs are ORed together */ > + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, > + "num-lines", &err); > + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, > + qdev_get_gpio_in(armv7m, ADC_IRQ)); > + > + dev = DEVICE(&(s->adc[i])); > + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, ADC_ADDR); > + sysbus_connect_irq(busdev, 0, > + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); > + > + /* SPI devices */ > + for (i = 0; i < STM_NUM_SPIS; i++) { > + dev = DEVICE(&(s->spi[i])); > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, spi_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); > + } > + > + /* EXTI device */ > + dev = DEVICE(&s->exti); > + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); > + if (err != NULL) { > + error_propagate(errp, err); > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, EXTI_ADDR); > + for (i = 0; i < 16; i++) { > + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); > + } > + for (i = 0; i < 16; i++) { > + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); > + } > + > + create_unimplemented_device("timer[6]", 0x40001000, 0x400 - 1); You shouldn't need to remove the last byte... > + create_unimplemented_device("timer[7]", 0x40001400, 0x400 - 1); > + create_unimplemented_device("timer[12]", 0x40001800, 0x400 - 1); > + create_unimplemented_device("timer[13]", 0x40001C00, 0x400 - 1); > + create_unimplemented_device("timer[14]", 0x40002000, 0x400 - 1); > + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400 - 1); > + create_unimplemented_device("WWDG", 0x40002C00, 0x400 - 1); > + create_unimplemented_device("IWDG", 0x40003000, 0x400 - 1); > + create_unimplemented_device("I2S2ext", 0x40003000, 0x400 - 1); > + create_unimplemented_device("I2S3ext", 0x40004000, 0x400 - 1); > + create_unimplemented_device("I2C1", 0x40005400, 0x400 - 1); > + create_unimplemented_device("I2C2", 0x40005800, 0x400 - 1); > + create_unimplemented_device("I2C3", 0x40005C00, 0x400 - 1); > + create_unimplemented_device("CAN1", 0x40006400, 0x400 - 1); > + create_unimplemented_device("CAN2", 0x40006800, 0x400 - 1); > + create_unimplemented_device("PWR", 0x40007000, 0x400 - 1); > + create_unimplemented_device("DAC", 0x40007400, 0x400 - 1); > + create_unimplemented_device("timer[1]", 0x40010000, 0x400 - 1); > + create_unimplemented_device("timer[8]", 0x40010400, 0x400 - 1); > + create_unimplemented_device("SDIO", 0x40012C00, 0x400 - 1); > + create_unimplemented_device("timer[9]", 0x40014000, 0x400 - 1); > + create_unimplemented_device("timer[10]", 0x40014400, 0x400 - 1); > + create_unimplemented_device("timer[11]", 0x40014800, 0x400 - 1); > + create_unimplemented_device("GPIOA", 0x40020000, 0x400 - 1); > + create_unimplemented_device("GPIOB", 0x40020400, 0x400 - 1); > + create_unimplemented_device("GPIOC", 0x40020800, 0x400 - 1); > + create_unimplemented_device("GPIOD", 0x40020C00, 0x400 - 1); > + create_unimplemented_device("GPIOE", 0x40021000, 0x400 - 1); > + create_unimplemented_device("GPIOF", 0x40021400, 0x400 - 1); > + create_unimplemented_device("GPIOG", 0x40021800, 0x400 - 1); > + create_unimplemented_device("GPIOH", 0x40021C00, 0x400 - 1); > + create_unimplemented_device("GPIOI", 0x40022000, 0x400 - 1); > + create_unimplemented_device("CRC", 0x40023000, 0x400 - 1); > + create_unimplemented_device("RCC", 0x40023800, 0x400 - 1); > + create_unimplemented_device("Flash Int", 0x40023C00, 0x400 - 1); > + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400 - 1); > + create_unimplemented_device("DMA1", 0x40026000, 0x400 - 1); > + create_unimplemented_device("DMA2", 0x40026400, 0x400 - 1); > + create_unimplemented_device("Ethernet", 0x40028000, 0x1400 - 1); > + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000 - 1); > + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000 - 1); > + create_unimplemented_device("DCMI", 0x50050000, 0x400 - 1); > + create_unimplemented_device("RNG", 0x50060800, 0x400 - 1); > +} > + > +static Property stm32f405_soc_properties[] = { > + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = stm32f405_soc_realize; > + dc->props = stm32f405_soc_properties; > +} > + > +static const TypeInfo stm32f405_soc_info = { > + .name = TYPE_STM32F405_SOC, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(STM32F405State), > + .instance_init = stm32f405_soc_initfn, > + .class_init = stm32f405_soc_class_init, > +}; > + > +static void stm32f405_soc_types(void) > +{ > + type_register_static(&stm32f405_soc_info); > +} > + > +type_init(stm32f405_soc_types) > diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h > new file mode 100644 > index 0000000000..f0aec53d32 > --- /dev/null > +++ b/include/hw/arm/stm32f405_soc.h > @@ -0,0 +1,70 @@ > +/* > + * STM32F405 SoC > + * > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_ARM_STM32F405_SOC_H > +#define HW_ARM_STM32F405_SOC_H > + > +#include "hw/misc/stm32f4xx_syscfg.h" > +#include "hw/timer/stm32f2xx_timer.h" > +#include "hw/char/stm32f2xx_usart.h" > +#include "hw/adc/stm32f2xx_adc.h" > +#include "hw/misc/stm32f4xx_exti.h" > +#include "hw/or-irq.h" > +#include "hw/ssi/stm32f2xx_spi.h" > +#include "hw/arm/armv7m.h" > + > +#define TYPE_STM32F405_SOC "stm32f405-soc" > +#define STM32F405_SOC(obj) \ > + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) > + > +#define STM_NUM_USARTS 7 > +#define STM_NUM_TIMERS 4 > +#define STM_NUM_ADCS 6 > +#define STM_NUM_SPIS 6 > + > +#define FLASH_BASE_ADDRESS 0x08000000 > +#define FLASH_SIZE (1024 * 1024) > +#define SRAM_BASE_ADDRESS 0x20000000 > +#define SRAM_SIZE (192 * 1024) > + > +typedef struct STM32F405State { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + char *cpu_type; > + > + ARMv7MState armv7m; > + > + STM32F4xxSyscfgState syscfg; > + STM32F4xxExtiState exti; > + STM32F2XXUsartState usart[STM_NUM_USARTS]; > + STM32F2XXTimerState timer[STM_NUM_TIMERS]; > + STM32F2XXADCState adc[STM_NUM_ADCS]; > + STM32F2XXSPIState spi[STM_NUM_SPIS]; > + > + qemu_or_irq *adc_irqs; > +} STM32F405State; > + > +#endif >
On Mon, Apr 29, 2019 at 5:38 AM KONRAD Frederic <frederic.konrad@adacore.com> wrote: > > Hi Alistair, > > Le 4/29/19 à 7:33 AM, Alistair Francis a écrit : > > Signed-off-by: Alistair Francis <alistair@alistair23.me> > > --- > > MAINTAINERS | 8 + > > default-configs/arm-softmmu.mak | 1 + > > hw/arm/Kconfig | 3 + > > hw/arm/Makefile.objs | 1 + > > hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ > > include/hw/arm/stm32f405_soc.h | 70 ++++++++ > > 6 files changed, 375 insertions(+) > > create mode 100644 hw/arm/stm32f405_soc.c > > create mode 100644 include/hw/arm/stm32f405_soc.h > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index dabbfccf9c..c9772735cf 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -803,6 +803,14 @@ F: hw/adc/* > > F: hw/ssi/stm32f2xx_spi.c > > F: include/hw/*/stm32*.h > > > > +STM32F405 > > +M: Alistair Francis <alistair@alistair23.me> > > +M: Peter Maydell <peter.maydell@linaro.org> > > +S: Maintained > > +F: hw/arm/stm32f405_soc.c > > +F: hw/misc/stm32f4xx_syscfg.c > > +F: hw/misc/stm32f4xx_exti.c > > + > > Netduino 2 > > M: Alistair Francis <alistair@alistair23.me> > > M: Peter Maydell <peter.maydell@linaro.org> > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > > index 8eb57de211..e079f10624 100644 > > --- a/default-configs/arm-softmmu.mak > > +++ b/default-configs/arm-softmmu.mak > > @@ -98,6 +98,7 @@ CONFIG_STM32F2XX_SPI=y > > CONFIG_STM32F205_SOC=y > > CONFIG_STM32F4XX_SYSCFG=y > > CONFIG_STM32F4XX_EXTI=y > > +CONFIG_STM32F405_SOC=y > > Why not using 4xx instead of 405 in this patch as well? I'm not sure if all the SoC variants are generic like that. Looking at the datasheet https://www.st.com/content/ccc/resource/technical/document/datasheet/ef/92/76/6d/bb/c2/4f/f7/DM00037051.pdf/files/DM00037051.pdf/jcr:content/translations/en.DM00037051.pdf it only specified the 405 and 407 variants. This is mostly a way just to say that I have tested it as a 405, it might work with others but I don't know. I think it's harder to make the SoC generic without having tested the other optinos (or knowing they are all interchangable). Alistair > > > CONFIG_NRF51_SOC=y > > > > CONFIG_CMSDK_APB_TIMER=y > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index d298fbdc89..3a98bce15a 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -62,6 +62,9 @@ config RASPI > > config STM32F205_SOC > > bool > > > > +config STM32F405_SOC > > + bool > > + > > config XLNX_ZYNQMP_ARM > > bool > > > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index fa57c7c770..36c3ff54c3 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -26,6 +26,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o > > obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o > > obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o > > obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o > > +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o > > obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o > > obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o > > obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o > > diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c > > new file mode 100644 > > index 0000000000..83adec51a2 > > --- /dev/null > > +++ b/hw/arm/stm32f405_soc.c > > @@ -0,0 +1,292 @@ > > +/* > > + * STM32F405 SoC > > + * > > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a copy > > + * of this software and associated documentation files (the "Software"), to deal > > + * in the Software without restriction, including without limitation the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qapi/error.h" > > +#include "qemu-common.h" > > +#include "hw/arm/arm.h" > > +#include "exec/address-spaces.h" > > +#include "hw/arm/stm32f405_soc.h" > > +#include "hw/misc/unimp.h" > > + > > +#define SYSCFG_ADD 0x40013800 > > +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, > > + 0x40004C00, 0x40005000, 0x40011400, > > + 0x40007800, 0x40007C00 }; > > +/* At the moment only Timer 2 to 5 are modelled */ > > +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, > > + 0x40000800, 0x40000C00 }; > > +#define ADC_ADDR 0x40012000 > > +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, > > + 0x40013400, 0x40015000, 0x40015400 }; > > +#define EXTI_ADDR 0x40013C00 > > + > > +#define SYSCFG_IRQ 71 > > +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; > > +static const int timer_irq[] = { 28, 29, 30, 50 }; > > +#define ADC_IRQ 18 > > +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; > > +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, > > + 40, 40, 40, 40, 40} ; > > + > > + > > +static void stm32f405_soc_initfn(Object *obj) > > +{ > > + STM32F405State *s = STM32F405_SOC(obj); > > + int i; > > + > > + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), > > + TYPE_ARMV7M); > > + > > + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), > > + TYPE_STM32F4XX_SYSCFG); > > + > > + for (i = 0; i < STM_NUM_USARTS; i++) { > > + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], > > + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); > > + } > > + > > + for (i = 0; i < STM_NUM_TIMERS; i++) { > > + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], > > + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); > > + } > > + > > + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); > > + > > + for (i = 0; i < STM_NUM_ADCS; i++) { > > + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), > > + TYPE_STM32F2XX_ADC); > > + } > > + > > + for (i = 0; i < STM_NUM_SPIS; i++) { > > + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), > > + TYPE_STM32F2XX_SPI); > > + } > > + > > + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), > > + TYPE_STM32F4XX_EXTI); > > +} > > + > > +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > > +{ > > + STM32F405State *s = STM32F405_SOC(dev_soc); > > + DeviceState *dev, *armv7m; > > + SysBusDevice *busdev; > > + Error *err = NULL; > > + int i; > > + > > + MemoryRegion *system_memory = get_system_memory(); > > + MemoryRegion *sram = g_new(MemoryRegion, 1); > > + MemoryRegion *flash = g_new(MemoryRegion, 1); > > + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); > > + > > + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, > > + &error_fatal); > > + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", > > + flash, 0, FLASH_SIZE); > > + > > + memory_region_set_readonly(flash, true); > > + memory_region_set_readonly(flash_alias, true); > > + > > + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); > > + memory_region_add_subregion(system_memory, 0, flash_alias); > > + > > + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, > > + &error_fatal); > > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > > + > > + armv7m = DEVICE(&s->armv7m); > > + qdev_prop_set_uint32(armv7m, "num-irq", 96); > > + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), > > + "memory", &error_abort); > > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + > > + /* System configuration controller */ > > + dev = DEVICE(&s->syscfg); > > + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); > > + > > + /* Attach UART (uses USART registers) and USART controllers */ > > + for (i = 0; i < STM_NUM_USARTS; i++) { > > + dev = DEVICE(&(s->usart[i])); > > + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); > > + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, usart_addr[i]); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); > > + } > > + > > + /* Timer 2 to 5 */ > > + for (i = 0; i < STM_NUM_TIMERS; i++) { > > + dev = DEVICE(&(s->timer[i])); > > + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); > > + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, timer_addr[i]); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); > > + } > > + > > + /* ADC device, the IRQs are ORed together */ > > + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, > > + "num-lines", &err); > > + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, > > + qdev_get_gpio_in(armv7m, ADC_IRQ)); > > + > > + dev = DEVICE(&(s->adc[i])); > > + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, ADC_ADDR); > > + sysbus_connect_irq(busdev, 0, > > + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); > > + > > + /* SPI devices */ > > + for (i = 0; i < STM_NUM_SPIS; i++) { > > + dev = DEVICE(&(s->spi[i])); > > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, spi_addr[i]); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); > > + } > > + > > + /* EXTI device */ > > + dev = DEVICE(&s->exti); > > + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, EXTI_ADDR); > > + for (i = 0; i < 16; i++) { > > + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); > > + } > > + for (i = 0; i < 16; i++) { > > + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); > > + } > > + > > + create_unimplemented_device("timer[6]", 0x40001000, 0x400 - 1); > > + create_unimplemented_device("timer[7]", 0x40001400, 0x400 - 1); > > + create_unimplemented_device("timer[12]", 0x40001800, 0x400 - 1); > > + create_unimplemented_device("timer[13]", 0x40001C00, 0x400 - 1); > > + create_unimplemented_device("timer[14]", 0x40002000, 0x400 - 1); > > + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400 - 1); > > + create_unimplemented_device("WWDG", 0x40002C00, 0x400 - 1); > > + create_unimplemented_device("IWDG", 0x40003000, 0x400 - 1); > > + create_unimplemented_device("I2S2ext", 0x40003000, 0x400 - 1); > > + create_unimplemented_device("I2S3ext", 0x40004000, 0x400 - 1); > > + create_unimplemented_device("I2C1", 0x40005400, 0x400 - 1); > > + create_unimplemented_device("I2C2", 0x40005800, 0x400 - 1); > > + create_unimplemented_device("I2C3", 0x40005C00, 0x400 - 1); > > + create_unimplemented_device("CAN1", 0x40006400, 0x400 - 1); > > + create_unimplemented_device("CAN2", 0x40006800, 0x400 - 1); > > + create_unimplemented_device("PWR", 0x40007000, 0x400 - 1); > > + create_unimplemented_device("DAC", 0x40007400, 0x400 - 1); > > + create_unimplemented_device("timer[1]", 0x40010000, 0x400 - 1); > > + create_unimplemented_device("timer[8]", 0x40010400, 0x400 - 1); > > + create_unimplemented_device("SDIO", 0x40012C00, 0x400 - 1); > > + create_unimplemented_device("timer[9]", 0x40014000, 0x400 - 1); > > + create_unimplemented_device("timer[10]", 0x40014400, 0x400 - 1); > > + create_unimplemented_device("timer[11]", 0x40014800, 0x400 - 1); > > + create_unimplemented_device("GPIOA", 0x40020000, 0x400 - 1); > > + create_unimplemented_device("GPIOB", 0x40020400, 0x400 - 1); > > + create_unimplemented_device("GPIOC", 0x40020800, 0x400 - 1); > > + create_unimplemented_device("GPIOD", 0x40020C00, 0x400 - 1); > > + create_unimplemented_device("GPIOE", 0x40021000, 0x400 - 1); > > + create_unimplemented_device("GPIOF", 0x40021400, 0x400 - 1); > > + create_unimplemented_device("GPIOG", 0x40021800, 0x400 - 1); > > + create_unimplemented_device("GPIOH", 0x40021C00, 0x400 - 1); > > + create_unimplemented_device("GPIOI", 0x40022000, 0x400 - 1); > > + create_unimplemented_device("CRC", 0x40023000, 0x400 - 1); > > + create_unimplemented_device("RCC", 0x40023800, 0x400 - 1); > > + create_unimplemented_device("Flash Int", 0x40023C00, 0x400 - 1); > > + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400 - 1); > > + create_unimplemented_device("DMA1", 0x40026000, 0x400 - 1); > > + create_unimplemented_device("DMA2", 0x40026400, 0x400 - 1); > > + create_unimplemented_device("Ethernet", 0x40028000, 0x1400 - 1); > > + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000 - 1); > > + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000 - 1); > > + create_unimplemented_device("DCMI", 0x50050000, 0x400 - 1); > > + create_unimplemented_device("RNG", 0x50060800, 0x400 - 1); > > +} > > + > > +static Property stm32f405_soc_properties[] = { > > + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc = DEVICE_CLASS(klass); > > + > > + dc->realize = stm32f405_soc_realize; > > + dc->props = stm32f405_soc_properties; > > +} > > + > > +static const TypeInfo stm32f405_soc_info = { > > + .name = TYPE_STM32F405_SOC, > > + .parent = TYPE_SYS_BUS_DEVICE, > > + .instance_size = sizeof(STM32F405State), > > + .instance_init = stm32f405_soc_initfn, > > + .class_init = stm32f405_soc_class_init, > > +}; > > + > > +static void stm32f405_soc_types(void) > > +{ > > + type_register_static(&stm32f405_soc_info); > > +} > > + > > +type_init(stm32f405_soc_types) > > diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h > > new file mode 100644 > > index 0000000000..f0aec53d32 > > --- /dev/null > > +++ b/include/hw/arm/stm32f405_soc.h > > @@ -0,0 +1,70 @@ > > +/* > > + * STM32F405 SoC > > + * > > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a copy > > + * of this software and associated documentation files (the "Software"), to deal > > + * in the Software without restriction, including without limitation the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#ifndef HW_ARM_STM32F405_SOC_H > > +#define HW_ARM_STM32F405_SOC_H > > + > > +#include "hw/misc/stm32f4xx_syscfg.h" > > +#include "hw/timer/stm32f2xx_timer.h" > > +#include "hw/char/stm32f2xx_usart.h" > > +#include "hw/adc/stm32f2xx_adc.h" > > +#include "hw/misc/stm32f4xx_exti.h" > > +#include "hw/or-irq.h" > > +#include "hw/ssi/stm32f2xx_spi.h" > > +#include "hw/arm/armv7m.h" > > + > > +#define TYPE_STM32F405_SOC "stm32f405-soc" > > +#define STM32F405_SOC(obj) \ > > + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) > > + > > +#define STM_NUM_USARTS 7 > > +#define STM_NUM_TIMERS 4 > > +#define STM_NUM_ADCS 6 > > +#define STM_NUM_SPIS 6 > > + > > +#define FLASH_BASE_ADDRESS 0x08000000 > > +#define FLASH_SIZE (1024 * 1024) > > +#define SRAM_BASE_ADDRESS 0x20000000 > > +#define SRAM_SIZE (192 * 1024) > > + > > +typedef struct STM32F405State { > > + /*< private >*/ > > + SysBusDevice parent_obj; > > + /*< public >*/ > > + > > + char *cpu_type; > > + > > + ARMv7MState armv7m; > > + > > + STM32F4xxSyscfgState syscfg; > > + STM32F4xxExtiState exti; > > + STM32F2XXUsartState usart[STM_NUM_USARTS]; > > + STM32F2XXTimerState timer[STM_NUM_TIMERS]; > > + STM32F2XXADCState adc[STM_NUM_ADCS]; > > + STM32F2XXSPIState spi[STM_NUM_SPIS]; > > + > > + qemu_or_irq *adc_irqs; > > +} STM32F405State; > > + > > +#endif > >
On Mon, Apr 29, 2019 at 5:43 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > On 4/29/19 7:33 AM, Alistair Francis wrote: > > Signed-off-by: Alistair Francis <alistair@alistair23.me> > > --- > > MAINTAINERS | 8 + > > default-configs/arm-softmmu.mak | 1 + > > hw/arm/Kconfig | 3 + > > hw/arm/Makefile.objs | 1 + > > hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ > > include/hw/arm/stm32f405_soc.h | 70 ++++++++ > > 6 files changed, 375 insertions(+) > > create mode 100644 hw/arm/stm32f405_soc.c > > create mode 100644 include/hw/arm/stm32f405_soc.h > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index dabbfccf9c..c9772735cf 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -803,6 +803,14 @@ F: hw/adc/* > > F: hw/ssi/stm32f2xx_spi.c > > F: include/hw/*/stm32*.h > > > > +STM32F405 > > +M: Alistair Francis <alistair@alistair23.me> > > +M: Peter Maydell <peter.maydell@linaro.org> > > +S: Maintained > > +F: hw/arm/stm32f405_soc.c > > +F: hw/misc/stm32f4xx_syscfg.c > > +F: hw/misc/stm32f4xx_exti.c > > + > > Netduino 2 > > M: Alistair Francis <alistair@alistair23.me> > > M: Peter Maydell <peter.maydell@linaro.org> > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak > > index 8eb57de211..e079f10624 100644 > > --- a/default-configs/arm-softmmu.mak > > +++ b/default-configs/arm-softmmu.mak > > @@ -98,6 +98,7 @@ CONFIG_STM32F2XX_SPI=y > > CONFIG_STM32F205_SOC=y > > CONFIG_STM32F4XX_SYSCFG=y > > CONFIG_STM32F4XX_EXTI=y > > +CONFIG_STM32F405_SOC=y > > CONFIG_NRF51_SOC=y > > > > CONFIG_CMSDK_APB_TIMER=y > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index d298fbdc89..3a98bce15a 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -62,6 +62,9 @@ config RASPI > > config STM32F205_SOC > > bool > > > > +config STM32F405_SOC > > + bool > > + > > config XLNX_ZYNQMP_ARM > > bool > > > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index fa57c7c770..36c3ff54c3 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -26,6 +26,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o > > obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o > > obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o > > obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o > > +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o > > obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o > > obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o > > obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o > > diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c > > new file mode 100644 > > index 0000000000..83adec51a2 > > --- /dev/null > > +++ b/hw/arm/stm32f405_soc.c > > @@ -0,0 +1,292 @@ > > +/* > > + * STM32F405 SoC > > + * > > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > > 2019? I never know how this works. It was originally written in 2014, do I update the year based on the upstream submission? > > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a copy > > + * of this software and associated documentation files (the "Software"), to deal > > + * in the Software without restriction, including without limitation the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qapi/error.h" > > +#include "qemu-common.h" > > +#include "hw/arm/arm.h" > > +#include "exec/address-spaces.h" > > +#include "hw/arm/stm32f405_soc.h" > > +#include "hw/misc/unimp.h" > > + > > +#define SYSCFG_ADD 0x40013800 > > +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, > > + 0x40004C00, 0x40005000, 0x40011400, > > + 0x40007800, 0x40007C00 }; > > +/* At the moment only Timer 2 to 5 are modelled */ > > +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, > > + 0x40000800, 0x40000C00 }; > > +#define ADC_ADDR 0x40012000 > > +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, > > + 0x40013400, 0x40015000, 0x40015400 }; > > +#define EXTI_ADDR 0x40013C00 > > + > > +#define SYSCFG_IRQ 71 > > +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; > > +static const int timer_irq[] = { 28, 29, 30, 50 }; > > +#define ADC_IRQ 18 > > +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; > > +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, > > + 40, 40, 40, 40, 40} ; > > + > > + > > +static void stm32f405_soc_initfn(Object *obj) > > +{ > > + STM32F405State *s = STM32F405_SOC(obj); > > + int i; > > + > > + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), > > + TYPE_ARMV7M); > > + > > + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), > > + TYPE_STM32F4XX_SYSCFG); > > + > > + for (i = 0; i < STM_NUM_USARTS; i++) { > > + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], > > + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); > > + } > > + > > + for (i = 0; i < STM_NUM_TIMERS; i++) { > > + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], > > + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); > > + } > > + > > + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); > > + > > + for (i = 0; i < STM_NUM_ADCS; i++) { > > + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), > > + TYPE_STM32F2XX_ADC); > > + } > > + > > + for (i = 0; i < STM_NUM_SPIS; i++) { > > + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), > > + TYPE_STM32F2XX_SPI); > > + } > > + > > + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), > > + TYPE_STM32F4XX_EXTI); > > +} > > + > > +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > > +{ > > + STM32F405State *s = STM32F405_SOC(dev_soc); > > + DeviceState *dev, *armv7m; > > + SysBusDevice *busdev; > > + Error *err = NULL; > > + int i; > > + > > + MemoryRegion *system_memory = get_system_memory(); > > + MemoryRegion *sram = g_new(MemoryRegion, 1); > > + MemoryRegion *flash = g_new(MemoryRegion, 1); > > + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); > > + > > + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, > > + &error_fatal); > > + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", > > + flash, 0, FLASH_SIZE); > > + > > + memory_region_set_readonly(flash, true); > > + memory_region_set_readonly(flash_alias, true); > > + > > + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); > > + memory_region_add_subregion(system_memory, 0, flash_alias); > > + > > + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, > > + &error_fatal); > > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > > + > > + armv7m = DEVICE(&s->armv7m); > > + qdev_prop_set_uint32(armv7m, "num-irq", 96); > > + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), > > + "memory", &error_abort); > > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + > > + /* System configuration controller */ > > + dev = DEVICE(&s->syscfg); > > + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); > > + > > + /* Attach UART (uses USART registers) and USART controllers */ > > + for (i = 0; i < STM_NUM_USARTS; i++) { > > + dev = DEVICE(&(s->usart[i])); > > + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); > > + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, usart_addr[i]); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); > > + } > > + > > + /* Timer 2 to 5 */ > > + for (i = 0; i < STM_NUM_TIMERS; i++) { > > + dev = DEVICE(&(s->timer[i])); > > + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); > > + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, timer_addr[i]); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); > > + } > > + > > + /* ADC device, the IRQs are ORed together */ > > + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, > > + "num-lines", &err); > > + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, > > + qdev_get_gpio_in(armv7m, ADC_IRQ)); > > + > > + dev = DEVICE(&(s->adc[i])); > > + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, ADC_ADDR); > > + sysbus_connect_irq(busdev, 0, > > + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); > > + > > + /* SPI devices */ > > + for (i = 0; i < STM_NUM_SPIS; i++) { > > + dev = DEVICE(&(s->spi[i])); > > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, spi_addr[i]); > > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); > > + } > > + > > + /* EXTI device */ > > + dev = DEVICE(&s->exti); > > + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); > > + if (err != NULL) { > > + error_propagate(errp, err); > > + return; > > + } > > + busdev = SYS_BUS_DEVICE(dev); > > + sysbus_mmio_map(busdev, 0, EXTI_ADDR); > > + for (i = 0; i < 16; i++) { > > + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); > > + } > > + for (i = 0; i < 16; i++) { > > + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); > > + } > > + > > + create_unimplemented_device("timer[6]", 0x40001000, 0x400 - 1); > > You shouldn't need to remove the last byte... Good point, I'll fix that. Alistair > > > + create_unimplemented_device("timer[7]", 0x40001400, 0x400 - 1); > > + create_unimplemented_device("timer[12]", 0x40001800, 0x400 - 1); > > + create_unimplemented_device("timer[13]", 0x40001C00, 0x400 - 1); > > + create_unimplemented_device("timer[14]", 0x40002000, 0x400 - 1); > > + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400 - 1); > > + create_unimplemented_device("WWDG", 0x40002C00, 0x400 - 1); > > + create_unimplemented_device("IWDG", 0x40003000, 0x400 - 1); > > + create_unimplemented_device("I2S2ext", 0x40003000, 0x400 - 1); > > + create_unimplemented_device("I2S3ext", 0x40004000, 0x400 - 1); > > + create_unimplemented_device("I2C1", 0x40005400, 0x400 - 1); > > + create_unimplemented_device("I2C2", 0x40005800, 0x400 - 1); > > + create_unimplemented_device("I2C3", 0x40005C00, 0x400 - 1); > > + create_unimplemented_device("CAN1", 0x40006400, 0x400 - 1); > > + create_unimplemented_device("CAN2", 0x40006800, 0x400 - 1); > > + create_unimplemented_device("PWR", 0x40007000, 0x400 - 1); > > + create_unimplemented_device("DAC", 0x40007400, 0x400 - 1); > > + create_unimplemented_device("timer[1]", 0x40010000, 0x400 - 1); > > + create_unimplemented_device("timer[8]", 0x40010400, 0x400 - 1); > > + create_unimplemented_device("SDIO", 0x40012C00, 0x400 - 1); > > + create_unimplemented_device("timer[9]", 0x40014000, 0x400 - 1); > > + create_unimplemented_device("timer[10]", 0x40014400, 0x400 - 1); > > + create_unimplemented_device("timer[11]", 0x40014800, 0x400 - 1); > > + create_unimplemented_device("GPIOA", 0x40020000, 0x400 - 1); > > + create_unimplemented_device("GPIOB", 0x40020400, 0x400 - 1); > > + create_unimplemented_device("GPIOC", 0x40020800, 0x400 - 1); > > + create_unimplemented_device("GPIOD", 0x40020C00, 0x400 - 1); > > + create_unimplemented_device("GPIOE", 0x40021000, 0x400 - 1); > > + create_unimplemented_device("GPIOF", 0x40021400, 0x400 - 1); > > + create_unimplemented_device("GPIOG", 0x40021800, 0x400 - 1); > > + create_unimplemented_device("GPIOH", 0x40021C00, 0x400 - 1); > > + create_unimplemented_device("GPIOI", 0x40022000, 0x400 - 1); > > + create_unimplemented_device("CRC", 0x40023000, 0x400 - 1); > > + create_unimplemented_device("RCC", 0x40023800, 0x400 - 1); > > + create_unimplemented_device("Flash Int", 0x40023C00, 0x400 - 1); > > + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400 - 1); > > + create_unimplemented_device("DMA1", 0x40026000, 0x400 - 1); > > + create_unimplemented_device("DMA2", 0x40026400, 0x400 - 1); > > + create_unimplemented_device("Ethernet", 0x40028000, 0x1400 - 1); > > + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000 - 1); > > + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000 - 1); > > + create_unimplemented_device("DCMI", 0x50050000, 0x400 - 1); > > + create_unimplemented_device("RNG", 0x50060800, 0x400 - 1); > > +} > > + > > +static Property stm32f405_soc_properties[] = { > > + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc = DEVICE_CLASS(klass); > > + > > + dc->realize = stm32f405_soc_realize; > > + dc->props = stm32f405_soc_properties; > > +} > > + > > +static const TypeInfo stm32f405_soc_info = { > > + .name = TYPE_STM32F405_SOC, > > + .parent = TYPE_SYS_BUS_DEVICE, > > + .instance_size = sizeof(STM32F405State), > > + .instance_init = stm32f405_soc_initfn, > > + .class_init = stm32f405_soc_class_init, > > +}; > > + > > +static void stm32f405_soc_types(void) > > +{ > > + type_register_static(&stm32f405_soc_info); > > +} > > + > > +type_init(stm32f405_soc_types) > > diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h > > new file mode 100644 > > index 0000000000..f0aec53d32 > > --- /dev/null > > +++ b/include/hw/arm/stm32f405_soc.h > > @@ -0,0 +1,70 @@ > > +/* > > + * STM32F405 SoC > > + * > > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a copy > > + * of this software and associated documentation files (the "Software"), to deal > > + * in the Software without restriction, including without limitation the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#ifndef HW_ARM_STM32F405_SOC_H > > +#define HW_ARM_STM32F405_SOC_H > > + > > +#include "hw/misc/stm32f4xx_syscfg.h" > > +#include "hw/timer/stm32f2xx_timer.h" > > +#include "hw/char/stm32f2xx_usart.h" > > +#include "hw/adc/stm32f2xx_adc.h" > > +#include "hw/misc/stm32f4xx_exti.h" > > +#include "hw/or-irq.h" > > +#include "hw/ssi/stm32f2xx_spi.h" > > +#include "hw/arm/armv7m.h" > > + > > +#define TYPE_STM32F405_SOC "stm32f405-soc" > > +#define STM32F405_SOC(obj) \ > > + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) > > + > > +#define STM_NUM_USARTS 7 > > +#define STM_NUM_TIMERS 4 > > +#define STM_NUM_ADCS 6 > > +#define STM_NUM_SPIS 6 > > + > > +#define FLASH_BASE_ADDRESS 0x08000000 > > +#define FLASH_SIZE (1024 * 1024) > > +#define SRAM_BASE_ADDRESS 0x20000000 > > +#define SRAM_SIZE (192 * 1024) > > + > > +typedef struct STM32F405State { > > + /*< private >*/ > > + SysBusDevice parent_obj; > > + /*< public >*/ > > + > > + char *cpu_type; > > + > > + ARMv7MState armv7m; > > + > > + STM32F4xxSyscfgState syscfg; > > + STM32F4xxExtiState exti; > > + STM32F2XXUsartState usart[STM_NUM_USARTS]; > > + STM32F2XXTimerState timer[STM_NUM_TIMERS]; > > + STM32F2XXADCState adc[STM_NUM_ADCS]; > > + STM32F2XXSPIState spi[STM_NUM_SPIS]; > > + > > + qemu_or_irq *adc_irqs; > > +} STM32F405State; > > + > > +#endif > >
On Mon, 29 Apr 2019 at 18:30, Alistair Francis <alistair23@gmail.com> wrote: > > On Mon, Apr 29, 2019 at 5:43 AM Philippe Mathieu-Daudé > <philmd@redhat.com> wrote: > > > > On 4/29/19 7:33 AM, Alistair Francis wrote: > > > --- /dev/null > > > +++ b/hw/arm/stm32f405_soc.c > > > @@ -0,0 +1,292 @@ > > > +/* > > > + * STM32F405 SoC > > > + * > > > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > > > > 2019? > > I never know how this works. It was originally written in 2014, do I > update the year based on the upstream submission? You could say "2014, 2019" if you like; or just use the date of original authorship. thanks -- PMM
On Mon, 29 Apr 2019 at 06:38, Alistair Francis <alistair@alistair23.me> wrote: > > Signed-off-by: Alistair Francis <alistair@alistair23.me> > --- > MAINTAINERS | 8 + > default-configs/arm-softmmu.mak | 1 + > hw/arm/Kconfig | 3 + > hw/arm/Makefile.objs | 1 + > hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ > include/hw/arm/stm32f405_soc.h | 70 ++++++++ > 6 files changed, 375 insertions(+) > create mode 100644 hw/arm/stm32f405_soc.c > create mode 100644 include/hw/arm/stm32f405_soc.h Looks good; a few minor things below. > +static void stm32f405_soc_initfn(Object *obj) > +{ > + STM32F405State *s = STM32F405_SOC(obj); > + int i; > + > + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), > + TYPE_ARMV7M); > + > + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), > + TYPE_STM32F4XX_SYSCFG); > + > + for (i = 0; i < STM_NUM_USARTS; i++) { > + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], > + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); > + } > + > + for (i = 0; i < STM_NUM_TIMERS; i++) { > + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], > + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); > + } > + > + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); It would be more in keeping with the style of the rest of this device to have the device be inline in the STM32F405State struct and initialized with object_initialize_child() rather than allocated separately with object_new(). (hw/arm/armsse.c has an example of doing this with a TYPE_OR_IRQ object.) > + > + for (i = 0; i < STM_NUM_ADCS; i++) { > + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), > + TYPE_STM32F2XX_ADC); > + } > + > + for (i = 0; i < STM_NUM_SPIS; i++) { > + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), > + TYPE_STM32F2XX_SPI); > + } > + > + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), > + TYPE_STM32F4XX_EXTI); > +} > + > +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > +{ > + STM32F405State *s = STM32F405_SOC(dev_soc); > + DeviceState *dev, *armv7m; > + SysBusDevice *busdev; > + Error *err = NULL; > + int i; > + > + MemoryRegion *system_memory = get_system_memory(); > + MemoryRegion *sram = g_new(MemoryRegion, 1); > + MemoryRegion *flash = g_new(MemoryRegion, 1); > + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); I would prefer to have these MemoryRegions be in the STM32F405State struct rather than separately allocated. > + > + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, > + &error_fatal); Better to pass the error back up via errp rather than use error_fatal in a realize function. > + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", > + flash, 0, FLASH_SIZE); > + > + memory_region_set_readonly(flash, true); > + memory_region_set_readonly(flash_alias, true); > + > + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); > + memory_region_add_subregion(system_memory, 0, flash_alias); > + > + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, > + &error_fatal); > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > + > + armv7m = DEVICE(&s->armv7m); > + qdev_prop_set_uint32(armv7m, "num-irq", 96); > + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), You could use OBJECT(system_memory) rather than calling get_system_memory() again. > +static Property stm32f405_soc_properties[] = { > + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = stm32f405_soc_realize; > + dc->props = stm32f405_soc_properties; A comment here "No vmstate or reset required: device has no internal state" would help indicate that dc->vmsd and dc->reset have not merely been forgotten. (Eventually I might actually write a patch to let us express in code "dc->vmsd = device_has_no_state;"...) > +} thanks -- PMM
Le 4/29/19 à 7:00 PM, Alistair Francis a écrit : > On Mon, Apr 29, 2019 at 5:38 AM KONRAD Frederic > <frederic.konrad@adacore.com> wrote: >> >> Hi Alistair, >> >> Le 4/29/19 à 7:33 AM, Alistair Francis a écrit : >>> Signed-off-by: Alistair Francis <alistair@alistair23.me> >>> --- >>> MAINTAINERS | 8 + >>> default-configs/arm-softmmu.mak | 1 + >>> hw/arm/Kconfig | 3 + >>> hw/arm/Makefile.objs | 1 + >>> hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ >>> include/hw/arm/stm32f405_soc.h | 70 ++++++++ >>> 6 files changed, 375 insertions(+) >>> create mode 100644 hw/arm/stm32f405_soc.c >>> create mode 100644 include/hw/arm/stm32f405_soc.h >>> >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index dabbfccf9c..c9772735cf 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -803,6 +803,14 @@ F: hw/adc/* >>> F: hw/ssi/stm32f2xx_spi.c >>> F: include/hw/*/stm32*.h >>> >>> +STM32F405 >>> +M: Alistair Francis <alistair@alistair23.me> >>> +M: Peter Maydell <peter.maydell@linaro.org> >>> +S: Maintained >>> +F: hw/arm/stm32f405_soc.c >>> +F: hw/misc/stm32f4xx_syscfg.c >>> +F: hw/misc/stm32f4xx_exti.c >>> + >>> Netduino 2 >>> M: Alistair Francis <alistair@alistair23.me> >>> M: Peter Maydell <peter.maydell@linaro.org> >>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak >>> index 8eb57de211..e079f10624 100644 >>> --- a/default-configs/arm-softmmu.mak >>> +++ b/default-configs/arm-softmmu.mak >>> @@ -98,6 +98,7 @@ CONFIG_STM32F2XX_SPI=y >>> CONFIG_STM32F205_SOC=y >>> CONFIG_STM32F4XX_SYSCFG=y >>> CONFIG_STM32F4XX_EXTI=y >>> +CONFIG_STM32F405_SOC=y >> >> Why not using 4xx instead of 405 in this patch as well? > > I'm not sure if all the SoC variants are generic like that. Looking at > the datasheet https://www.st.com/content/ccc/resource/technical/document/datasheet/ef/92/76/6d/bb/c2/4f/f7/DM00037051.pdf/files/DM00037051.pdf/jcr:content/translations/en.DM00037051.pdf > it only specified the 405 and 407 variants. This is mostly a way just > to say that I have tested it as a 405, it might work with others but I > don't know. I think it's harder to make the SoC generic without having > tested the other optinos (or knowing they are all interchangable). Ok makes sense. I was wondering because you pass a cpu_type property and your commit message mention "STM32F4xx". > > Alistair > >> >>> CONFIG_NRF51_SOC=y >>> >>> CONFIG_CMSDK_APB_TIMER=y >>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig >>> index d298fbdc89..3a98bce15a 100644 >>> --- a/hw/arm/Kconfig >>> +++ b/hw/arm/Kconfig >>> @@ -62,6 +62,9 @@ config RASPI >>> config STM32F205_SOC >>> bool >>> >>> +config STM32F405_SOC >>> + bool >>> + >>> config XLNX_ZYNQMP_ARM >>> bool >>> >>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs >>> index fa57c7c770..36c3ff54c3 100644 >>> --- a/hw/arm/Makefile.objs >>> +++ b/hw/arm/Makefile.objs >>> @@ -26,6 +26,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o >>> obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o >>> obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o >>> obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o >>> +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o >>> obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o >>> obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o >>> obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o >>> diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c >>> new file mode 100644 >>> index 0000000000..83adec51a2 >>> --- /dev/null >>> +++ b/hw/arm/stm32f405_soc.c >>> @@ -0,0 +1,292 @@ >>> +/* >>> + * STM32F405 SoC >>> + * >>> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> >>> + * >>> + * Permission is hereby granted, free of charge, to any person obtaining a copy >>> + * of this software and associated documentation files (the "Software"), to deal >>> + * in the Software without restriction, including without limitation the rights >>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell >>> + * copies of the Software, and to permit persons to whom the Software is >>> + * furnished to do so, subject to the following conditions: >>> + * >>> + * The above copyright notice and this permission notice shall be included in >>> + * all copies or substantial portions of the Software. >>> + * >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER >>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, >>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN >>> + * THE SOFTWARE. >>> + */ >>> + >>> +#include "qemu/osdep.h" >>> +#include "qapi/error.h" >>> +#include "qemu-common.h" >>> +#include "hw/arm/arm.h" >>> +#include "exec/address-spaces.h" >>> +#include "hw/arm/stm32f405_soc.h" >>> +#include "hw/misc/unimp.h" >>> + >>> +#define SYSCFG_ADD 0x40013800 >>> +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, >>> + 0x40004C00, 0x40005000, 0x40011400, >>> + 0x40007800, 0x40007C00 }; >>> +/* At the moment only Timer 2 to 5 are modelled */ >>> +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, >>> + 0x40000800, 0x40000C00 }; >>> +#define ADC_ADDR 0x40012000 >>> +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, >>> + 0x40013400, 0x40015000, 0x40015400 }; >>> +#define EXTI_ADDR 0x40013C00 >>> + >>> +#define SYSCFG_IRQ 71 >>> +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; >>> +static const int timer_irq[] = { 28, 29, 30, 50 }; >>> +#define ADC_IRQ 18 >>> +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; >>> +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, >>> + 40, 40, 40, 40, 40} ; >>> + >>> + >>> +static void stm32f405_soc_initfn(Object *obj) >>> +{ >>> + STM32F405State *s = STM32F405_SOC(obj); >>> + int i; >>> + >>> + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), >>> + TYPE_ARMV7M); >>> + >>> + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), >>> + TYPE_STM32F4XX_SYSCFG); >>> + >>> + for (i = 0; i < STM_NUM_USARTS; i++) { >>> + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], >>> + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); >>> + } >>> + >>> + for (i = 0; i < STM_NUM_TIMERS; i++) { >>> + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], >>> + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); >>> + } >>> + >>> + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); >>> + >>> + for (i = 0; i < STM_NUM_ADCS; i++) { >>> + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), >>> + TYPE_STM32F2XX_ADC); >>> + } >>> + >>> + for (i = 0; i < STM_NUM_SPIS; i++) { >>> + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), >>> + TYPE_STM32F2XX_SPI); >>> + } >>> + >>> + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), >>> + TYPE_STM32F4XX_EXTI); >>> +} >>> + >>> +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) >>> +{ >>> + STM32F405State *s = STM32F405_SOC(dev_soc); >>> + DeviceState *dev, *armv7m; >>> + SysBusDevice *busdev; >>> + Error *err = NULL; >>> + int i; >>> + >>> + MemoryRegion *system_memory = get_system_memory(); >>> + MemoryRegion *sram = g_new(MemoryRegion, 1); >>> + MemoryRegion *flash = g_new(MemoryRegion, 1); >>> + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); >>> + >>> + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, >>> + &error_fatal); >>> + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", >>> + flash, 0, FLASH_SIZE); >>> + >>> + memory_region_set_readonly(flash, true); >>> + memory_region_set_readonly(flash_alias, true); >>> + >>> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); >>> + memory_region_add_subregion(system_memory, 0, flash_alias); >>> + >>> + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, >>> + &error_fatal); >>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); >>> + >>> + armv7m = DEVICE(&s->armv7m); >>> + qdev_prop_set_uint32(armv7m, "num-irq", 96); >>> + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); >>> + qdev_prop_set_bit(armv7m, "enable-bitband", true); >>> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), >>> + "memory", &error_abort); >>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + >>> + /* System configuration controller */ >>> + dev = DEVICE(&s->syscfg); >>> + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + busdev = SYS_BUS_DEVICE(dev); >>> + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); >>> + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); >>> + >>> + /* Attach UART (uses USART registers) and USART controllers */ >>> + for (i = 0; i < STM_NUM_USARTS; i++) { >>> + dev = DEVICE(&(s->usart[i])); >>> + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); >>> + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + busdev = SYS_BUS_DEVICE(dev); >>> + sysbus_mmio_map(busdev, 0, usart_addr[i]); >>> + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); >>> + } >>> + >>> + /* Timer 2 to 5 */ >>> + for (i = 0; i < STM_NUM_TIMERS; i++) { >>> + dev = DEVICE(&(s->timer[i])); >>> + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); >>> + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + busdev = SYS_BUS_DEVICE(dev); >>> + sysbus_mmio_map(busdev, 0, timer_addr[i]); >>> + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); >>> + } >>> + >>> + /* ADC device, the IRQs are ORed together */ >>> + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, >>> + "num-lines", &err); >>> + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, >>> + qdev_get_gpio_in(armv7m, ADC_IRQ)); >>> + >>> + dev = DEVICE(&(s->adc[i])); >>> + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + busdev = SYS_BUS_DEVICE(dev); >>> + sysbus_mmio_map(busdev, 0, ADC_ADDR); >>> + sysbus_connect_irq(busdev, 0, >>> + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); >>> + >>> + /* SPI devices */ >>> + for (i = 0; i < STM_NUM_SPIS; i++) { >>> + dev = DEVICE(&(s->spi[i])); >>> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + busdev = SYS_BUS_DEVICE(dev); >>> + sysbus_mmio_map(busdev, 0, spi_addr[i]); >>> + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); >>> + } >>> + >>> + /* EXTI device */ >>> + dev = DEVICE(&s->exti); >>> + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); >>> + if (err != NULL) { >>> + error_propagate(errp, err); >>> + return; >>> + } >>> + busdev = SYS_BUS_DEVICE(dev); >>> + sysbus_mmio_map(busdev, 0, EXTI_ADDR); >>> + for (i = 0; i < 16; i++) { >>> + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); >>> + } >>> + for (i = 0; i < 16; i++) { >>> + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); >>> + } >>> + >>> + create_unimplemented_device("timer[6]", 0x40001000, 0x400 - 1); >>> + create_unimplemented_device("timer[7]", 0x40001400, 0x400 - 1); >>> + create_unimplemented_device("timer[12]", 0x40001800, 0x400 - 1); >>> + create_unimplemented_device("timer[13]", 0x40001C00, 0x400 - 1); >>> + create_unimplemented_device("timer[14]", 0x40002000, 0x400 - 1); >>> + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400 - 1); >>> + create_unimplemented_device("WWDG", 0x40002C00, 0x400 - 1); >>> + create_unimplemented_device("IWDG", 0x40003000, 0x400 - 1); >>> + create_unimplemented_device("I2S2ext", 0x40003000, 0x400 - 1); >>> + create_unimplemented_device("I2S3ext", 0x40004000, 0x400 - 1); >>> + create_unimplemented_device("I2C1", 0x40005400, 0x400 - 1); >>> + create_unimplemented_device("I2C2", 0x40005800, 0x400 - 1); >>> + create_unimplemented_device("I2C3", 0x40005C00, 0x400 - 1); >>> + create_unimplemented_device("CAN1", 0x40006400, 0x400 - 1); >>> + create_unimplemented_device("CAN2", 0x40006800, 0x400 - 1); >>> + create_unimplemented_device("PWR", 0x40007000, 0x400 - 1); >>> + create_unimplemented_device("DAC", 0x40007400, 0x400 - 1); >>> + create_unimplemented_device("timer[1]", 0x40010000, 0x400 - 1); >>> + create_unimplemented_device("timer[8]", 0x40010400, 0x400 - 1); >>> + create_unimplemented_device("SDIO", 0x40012C00, 0x400 - 1); >>> + create_unimplemented_device("timer[9]", 0x40014000, 0x400 - 1); >>> + create_unimplemented_device("timer[10]", 0x40014400, 0x400 - 1); >>> + create_unimplemented_device("timer[11]", 0x40014800, 0x400 - 1); >>> + create_unimplemented_device("GPIOA", 0x40020000, 0x400 - 1); >>> + create_unimplemented_device("GPIOB", 0x40020400, 0x400 - 1); >>> + create_unimplemented_device("GPIOC", 0x40020800, 0x400 - 1); >>> + create_unimplemented_device("GPIOD", 0x40020C00, 0x400 - 1); >>> + create_unimplemented_device("GPIOE", 0x40021000, 0x400 - 1); >>> + create_unimplemented_device("GPIOF", 0x40021400, 0x400 - 1); >>> + create_unimplemented_device("GPIOG", 0x40021800, 0x400 - 1); >>> + create_unimplemented_device("GPIOH", 0x40021C00, 0x400 - 1); >>> + create_unimplemented_device("GPIOI", 0x40022000, 0x400 - 1); >>> + create_unimplemented_device("CRC", 0x40023000, 0x400 - 1); >>> + create_unimplemented_device("RCC", 0x40023800, 0x400 - 1); >>> + create_unimplemented_device("Flash Int", 0x40023C00, 0x400 - 1); >>> + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400 - 1); >>> + create_unimplemented_device("DMA1", 0x40026000, 0x400 - 1); >>> + create_unimplemented_device("DMA2", 0x40026400, 0x400 - 1); >>> + create_unimplemented_device("Ethernet", 0x40028000, 0x1400 - 1); >>> + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000 - 1); >>> + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000 - 1); >>> + create_unimplemented_device("DCMI", 0x50050000, 0x400 - 1); >>> + create_unimplemented_device("RNG", 0x50060800, 0x400 - 1); >>> +} >>> + >>> +static Property stm32f405_soc_properties[] = { >>> + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), >>> + DEFINE_PROP_END_OF_LIST(), >>> +}; >>> + >>> +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) >>> +{ >>> + DeviceClass *dc = DEVICE_CLASS(klass); >>> + >>> + dc->realize = stm32f405_soc_realize; >>> + dc->props = stm32f405_soc_properties; >>> +} >>> + >>> +static const TypeInfo stm32f405_soc_info = { >>> + .name = TYPE_STM32F405_SOC, >>> + .parent = TYPE_SYS_BUS_DEVICE, >>> + .instance_size = sizeof(STM32F405State), >>> + .instance_init = stm32f405_soc_initfn, >>> + .class_init = stm32f405_soc_class_init, >>> +}; >>> + >>> +static void stm32f405_soc_types(void) >>> +{ >>> + type_register_static(&stm32f405_soc_info); >>> +} >>> + >>> +type_init(stm32f405_soc_types) >>> diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h >>> new file mode 100644 >>> index 0000000000..f0aec53d32 >>> --- /dev/null >>> +++ b/include/hw/arm/stm32f405_soc.h >>> @@ -0,0 +1,70 @@ >>> +/* >>> + * STM32F405 SoC >>> + * >>> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> >>> + * >>> + * Permission is hereby granted, free of charge, to any person obtaining a copy >>> + * of this software and associated documentation files (the "Software"), to deal >>> + * in the Software without restriction, including without limitation the rights >>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell >>> + * copies of the Software, and to permit persons to whom the Software is >>> + * furnished to do so, subject to the following conditions: >>> + * >>> + * The above copyright notice and this permission notice shall be included in >>> + * all copies or substantial portions of the Software. >>> + * >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER >>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, >>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN >>> + * THE SOFTWARE. >>> + */ >>> + >>> +#ifndef HW_ARM_STM32F405_SOC_H >>> +#define HW_ARM_STM32F405_SOC_H >>> + >>> +#include "hw/misc/stm32f4xx_syscfg.h" >>> +#include "hw/timer/stm32f2xx_timer.h" >>> +#include "hw/char/stm32f2xx_usart.h" >>> +#include "hw/adc/stm32f2xx_adc.h" >>> +#include "hw/misc/stm32f4xx_exti.h" >>> +#include "hw/or-irq.h" >>> +#include "hw/ssi/stm32f2xx_spi.h" >>> +#include "hw/arm/armv7m.h" >>> + >>> +#define TYPE_STM32F405_SOC "stm32f405-soc" >>> +#define STM32F405_SOC(obj) \ >>> + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) >>> + >>> +#define STM_NUM_USARTS 7 >>> +#define STM_NUM_TIMERS 4 >>> +#define STM_NUM_ADCS 6 >>> +#define STM_NUM_SPIS 6 >>> + >>> +#define FLASH_BASE_ADDRESS 0x08000000 >>> +#define FLASH_SIZE (1024 * 1024) >>> +#define SRAM_BASE_ADDRESS 0x20000000 >>> +#define SRAM_SIZE (192 * 1024) >>> + >>> +typedef struct STM32F405State { >>> + /*< private >*/ >>> + SysBusDevice parent_obj; >>> + /*< public >*/ >>> + >>> + char *cpu_type; >>> + >>> + ARMv7MState armv7m; >>> + >>> + STM32F4xxSyscfgState syscfg; >>> + STM32F4xxExtiState exti; >>> + STM32F2XXUsartState usart[STM_NUM_USARTS]; >>> + STM32F2XXTimerState timer[STM_NUM_TIMERS]; >>> + STM32F2XXADCState adc[STM_NUM_ADCS]; >>> + STM32F2XXSPIState spi[STM_NUM_SPIS]; >>> + >>> + qemu_or_irq *adc_irqs; >>> +} STM32F405State; >>> + >>> +#endif >>>
On Tue, Apr 30, 2019 at 8:59 AM Peter Maydell <peter.maydell@linaro.org> wrote: > > On Mon, 29 Apr 2019 at 06:38, Alistair Francis <alistair@alistair23.me> wrote: > > > > Signed-off-by: Alistair Francis <alistair@alistair23.me> > > --- > > MAINTAINERS | 8 + > > default-configs/arm-softmmu.mak | 1 + > > hw/arm/Kconfig | 3 + > > hw/arm/Makefile.objs | 1 + > > hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ > > include/hw/arm/stm32f405_soc.h | 70 ++++++++ > > 6 files changed, 375 insertions(+) > > create mode 100644 hw/arm/stm32f405_soc.c > > create mode 100644 include/hw/arm/stm32f405_soc.h > > Looks good; a few minor things below. > > > +static void stm32f405_soc_initfn(Object *obj) > > +{ > > + STM32F405State *s = STM32F405_SOC(obj); > > + int i; > > + > > + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), > > + TYPE_ARMV7M); > > + > > + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), > > + TYPE_STM32F4XX_SYSCFG); > > + > > + for (i = 0; i < STM_NUM_USARTS; i++) { > > + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], > > + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); > > + } > > + > > + for (i = 0; i < STM_NUM_TIMERS; i++) { > > + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], > > + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); > > + } > > + > > + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); > > It would be more in keeping with the style of the rest of this > device to have the device be inline in the STM32F405State > struct and initialized with object_initialize_child() rather > than allocated separately with object_new(). (hw/arm/armsse.c > has an example of doing this with a TYPE_OR_IRQ object.) I have addressed all your comments. Alistair > > > + > > + for (i = 0; i < STM_NUM_ADCS; i++) { > > + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), > > + TYPE_STM32F2XX_ADC); > > + } > > + > > + for (i = 0; i < STM_NUM_SPIS; i++) { > > + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), > > + TYPE_STM32F2XX_SPI); > > + } > > + > > + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), > > + TYPE_STM32F4XX_EXTI); > > +} > > + > > +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > > +{ > > + STM32F405State *s = STM32F405_SOC(dev_soc); > > + DeviceState *dev, *armv7m; > > + SysBusDevice *busdev; > > + Error *err = NULL; > > + int i; > > + > > + MemoryRegion *system_memory = get_system_memory(); > > + MemoryRegion *sram = g_new(MemoryRegion, 1); > > + MemoryRegion *flash = g_new(MemoryRegion, 1); > > + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); > > I would prefer to have these MemoryRegions be in the STM32F405State > struct rather than separately allocated. > > > + > > + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, > > + &error_fatal); > > Better to pass the error back up via errp rather than use error_fatal > in a realize function. > > > + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", > > + flash, 0, FLASH_SIZE); > > + > > + memory_region_set_readonly(flash, true); > > + memory_region_set_readonly(flash_alias, true); > > + > > + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); > > + memory_region_add_subregion(system_memory, 0, flash_alias); > > + > > + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, > > + &error_fatal); > > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > > + > > + armv7m = DEVICE(&s->armv7m); > > + qdev_prop_set_uint32(armv7m, "num-irq", 96); > > + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > > + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), > > You could use OBJECT(system_memory) rather than calling > get_system_memory() again. > > > +static Property stm32f405_soc_properties[] = { > > + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc = DEVICE_CLASS(klass); > > + > > + dc->realize = stm32f405_soc_realize; > > + dc->props = stm32f405_soc_properties; > > A comment here "No vmstate or reset required: device has no internal state" > would help indicate that dc->vmsd and dc->reset have not merely > been forgotten. > > (Eventually I might actually write a patch to let us express > in code "dc->vmsd = device_has_no_state;"...) > > > +} > > thanks > -- PMM
diff --git a/MAINTAINERS b/MAINTAINERS index dabbfccf9c..c9772735cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -803,6 +803,14 @@ F: hw/adc/* F: hw/ssi/stm32f2xx_spi.c F: include/hw/*/stm32*.h +STM32F405 +M: Alistair Francis <alistair@alistair23.me> +M: Peter Maydell <peter.maydell@linaro.org> +S: Maintained +F: hw/arm/stm32f405_soc.c +F: hw/misc/stm32f4xx_syscfg.c +F: hw/misc/stm32f4xx_exti.c + Netduino 2 M: Alistair Francis <alistair@alistair23.me> M: Peter Maydell <peter.maydell@linaro.org> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 8eb57de211..e079f10624 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -98,6 +98,7 @@ CONFIG_STM32F2XX_SPI=y CONFIG_STM32F205_SOC=y CONFIG_STM32F4XX_SYSCFG=y CONFIG_STM32F4XX_EXTI=y +CONFIG_STM32F405_SOC=y CONFIG_NRF51_SOC=y CONFIG_CMSDK_APB_TIMER=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d298fbdc89..3a98bce15a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -62,6 +62,9 @@ config RASPI config STM32F205_SOC bool +config STM32F405_SOC + bool + config XLNX_ZYNQMP_ARM bool diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fa57c7c770..36c3ff54c3 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -26,6 +26,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c new file mode 100644 index 0000000000..83adec51a2 --- /dev/null +++ b/hw/arm/stm32f405_soc.c @@ -0,0 +1,292 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/misc/unimp.h" + +#define SYSCFG_ADD 0x40013800 +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, + 0x40004C00, 0x40005000, 0x40011400, + 0x40007800, 0x40007C00 }; +/* At the moment only Timer 2 to 5 are modelled */ +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, + 0x40000800, 0x40000C00 }; +#define ADC_ADDR 0x40012000 +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, + 0x40013400, 0x40015000, 0x40015400 }; +#define EXTI_ADDR 0x40013C00 + +#define SYSCFG_IRQ 71 +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; +static const int timer_irq[] = { 28, 29, 30, 50 }; +#define ADC_IRQ 18 +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, + 40, 40, 40, 40, 40} ; + + +static void stm32f405_soc_initfn(Object *obj) +{ + STM32F405State *s = STM32F405_SOC(obj); + int i; + + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), + TYPE_ARMV7M); + + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), + TYPE_STM32F4XX_SYSCFG); + + for (i = 0; i < STM_NUM_USARTS; i++) { + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); + } + + for (i = 0; i < STM_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); + } + + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); + + for (i = 0; i < STM_NUM_ADCS; i++) { + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), + TYPE_STM32F2XX_ADC); + } + + for (i = 0; i < STM_NUM_SPIS; i++) { + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), + TYPE_STM32F2XX_SPI); + } + + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), + TYPE_STM32F4XX_EXTI); +} + +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) +{ + STM32F405State *s = STM32F405_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err = NULL; + int i; + + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *sram = g_new(MemoryRegion, 1); + MemoryRegion *flash = g_new(MemoryRegion, 1); + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); + + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, + &error_fatal); + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", + flash, 0, FLASH_SIZE); + + memory_region_set_readonly(flash, true); + memory_region_set_readonly(flash_alias, true); + + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); + memory_region_add_subregion(system_memory, 0, flash_alias); + + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, + &error_fatal); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + armv7m = DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + /* System configuration controller */ + dev = DEVICE(&s->syscfg); + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); + + /* Attach UART (uses USART registers) and USART controllers */ + for (i = 0; i < STM_NUM_USARTS; i++) { + dev = DEVICE(&(s->usart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, usart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); + } + + /* Timer 2 to 5 */ + for (i = 0; i < STM_NUM_TIMERS; i++) { + dev = DEVICE(&(s->timer[i])); + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, timer_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); + } + + /* ADC device, the IRQs are ORed together */ + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, + "num-lines", &err); + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, + qdev_get_gpio_in(armv7m, ADC_IRQ)); + + dev = DEVICE(&(s->adc[i])); + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, ADC_ADDR); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); + + /* SPI devices */ + for (i = 0; i < STM_NUM_SPIS; i++) { + dev = DEVICE(&(s->spi[i])); + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); + } + + /* EXTI device */ + dev = DEVICE(&s->exti); + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, EXTI_ADDR); + for (i = 0; i < 16; i++) { + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); + } + for (i = 0; i < 16; i++) { + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); + } + + create_unimplemented_device("timer[6]", 0x40001000, 0x400 - 1); + create_unimplemented_device("timer[7]", 0x40001400, 0x400 - 1); + create_unimplemented_device("timer[12]", 0x40001800, 0x400 - 1); + create_unimplemented_device("timer[13]", 0x40001C00, 0x400 - 1); + create_unimplemented_device("timer[14]", 0x40002000, 0x400 - 1); + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400 - 1); + create_unimplemented_device("WWDG", 0x40002C00, 0x400 - 1); + create_unimplemented_device("IWDG", 0x40003000, 0x400 - 1); + create_unimplemented_device("I2S2ext", 0x40003000, 0x400 - 1); + create_unimplemented_device("I2S3ext", 0x40004000, 0x400 - 1); + create_unimplemented_device("I2C1", 0x40005400, 0x400 - 1); + create_unimplemented_device("I2C2", 0x40005800, 0x400 - 1); + create_unimplemented_device("I2C3", 0x40005C00, 0x400 - 1); + create_unimplemented_device("CAN1", 0x40006400, 0x400 - 1); + create_unimplemented_device("CAN2", 0x40006800, 0x400 - 1); + create_unimplemented_device("PWR", 0x40007000, 0x400 - 1); + create_unimplemented_device("DAC", 0x40007400, 0x400 - 1); + create_unimplemented_device("timer[1]", 0x40010000, 0x400 - 1); + create_unimplemented_device("timer[8]", 0x40010400, 0x400 - 1); + create_unimplemented_device("SDIO", 0x40012C00, 0x400 - 1); + create_unimplemented_device("timer[9]", 0x40014000, 0x400 - 1); + create_unimplemented_device("timer[10]", 0x40014400, 0x400 - 1); + create_unimplemented_device("timer[11]", 0x40014800, 0x400 - 1); + create_unimplemented_device("GPIOA", 0x40020000, 0x400 - 1); + create_unimplemented_device("GPIOB", 0x40020400, 0x400 - 1); + create_unimplemented_device("GPIOC", 0x40020800, 0x400 - 1); + create_unimplemented_device("GPIOD", 0x40020C00, 0x400 - 1); + create_unimplemented_device("GPIOE", 0x40021000, 0x400 - 1); + create_unimplemented_device("GPIOF", 0x40021400, 0x400 - 1); + create_unimplemented_device("GPIOG", 0x40021800, 0x400 - 1); + create_unimplemented_device("GPIOH", 0x40021C00, 0x400 - 1); + create_unimplemented_device("GPIOI", 0x40022000, 0x400 - 1); + create_unimplemented_device("CRC", 0x40023000, 0x400 - 1); + create_unimplemented_device("RCC", 0x40023800, 0x400 - 1); + create_unimplemented_device("Flash Int", 0x40023C00, 0x400 - 1); + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400 - 1); + create_unimplemented_device("DMA1", 0x40026000, 0x400 - 1); + create_unimplemented_device("DMA2", 0x40026400, 0x400 - 1); + create_unimplemented_device("Ethernet", 0x40028000, 0x1400 - 1); + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000 - 1); + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000 - 1); + create_unimplemented_device("DCMI", 0x50050000, 0x400 - 1); + create_unimplemented_device("RNG", 0x50060800, 0x400 - 1); +} + +static Property stm32f405_soc_properties[] = { + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = stm32f405_soc_realize; + dc->props = stm32f405_soc_properties; +} + +static const TypeInfo stm32f405_soc_info = { + .name = TYPE_STM32F405_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F405State), + .instance_init = stm32f405_soc_initfn, + .class_init = stm32f405_soc_class_init, +}; + +static void stm32f405_soc_types(void) +{ + type_register_static(&stm32f405_soc_info); +} + +type_init(stm32f405_soc_types) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h new file mode 100644 index 0000000000..f0aec53d32 --- /dev/null +++ b/include/hw/arm/stm32f405_soc.h @@ -0,0 +1,70 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_STM32F405_SOC_H +#define HW_ARM_STM32F405_SOC_H + +#include "hw/misc/stm32f4xx_syscfg.h" +#include "hw/timer/stm32f2xx_timer.h" +#include "hw/char/stm32f2xx_usart.h" +#include "hw/adc/stm32f2xx_adc.h" +#include "hw/misc/stm32f4xx_exti.h" +#include "hw/or-irq.h" +#include "hw/ssi/stm32f2xx_spi.h" +#include "hw/arm/armv7m.h" + +#define TYPE_STM32F405_SOC "stm32f405-soc" +#define STM32F405_SOC(obj) \ + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) + +#define STM_NUM_USARTS 7 +#define STM_NUM_TIMERS 4 +#define STM_NUM_ADCS 6 +#define STM_NUM_SPIS 6 + +#define FLASH_BASE_ADDRESS 0x08000000 +#define FLASH_SIZE (1024 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (192 * 1024) + +typedef struct STM32F405State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + char *cpu_type; + + ARMv7MState armv7m; + + STM32F4xxSyscfgState syscfg; + STM32F4xxExtiState exti; + STM32F2XXUsartState usart[STM_NUM_USARTS]; + STM32F2XXTimerState timer[STM_NUM_TIMERS]; + STM32F2XXADCState adc[STM_NUM_ADCS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; + + qemu_or_irq *adc_irqs; +} STM32F405State; + +#endif
Signed-off-by: Alistair Francis <alistair@alistair23.me> --- MAINTAINERS | 8 + default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 3 + hw/arm/Makefile.objs | 1 + hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ include/hw/arm/stm32f405_soc.h | 70 ++++++++ 6 files changed, 375 insertions(+) create mode 100644 hw/arm/stm32f405_soc.c create mode 100644 include/hw/arm/stm32f405_soc.h