From patchwork Tue Feb 28 10:30:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 143393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4ECDDB6FA2 for ; Tue, 28 Feb 2012 21:31:44 +1100 (EST) Received: from localhost ([::1]:47949 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2KLK-0004n7-S3 for incoming@patchwork.ozlabs.org; Tue, 28 Feb 2012 05:31:38 -0500 Received: from eggs.gnu.org ([208.118.235.92]:46917) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2KL8-0004mh-5h for qemu-devel@nongnu.org; Tue, 28 Feb 2012 05:31:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S2KKs-0005my-Iu for qemu-devel@nongnu.org; Tue, 28 Feb 2012 05:31:25 -0500 Received: from mga03.intel.com ([143.182.124.21]:15717) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2KKs-0005ma-53 for qemu-devel@nongnu.org; Tue, 28 Feb 2012 05:31:10 -0500 Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga101.ch.intel.com with ESMTP; 28 Feb 2012 02:31:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.71,315,1320652800"; d="scan'208,223"; a="71258835" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by AZSMGA002.ch.intel.com with ESMTP; 28 Feb 2012 02:30:59 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by PGSMSX102.gar.corp.intel.com (10.221.44.80) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 28 Feb 2012 18:30:58 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.142]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.91]) with mapi id 14.01.0355.002; Tue, 28 Feb 2012 18:30:56 +0800 From: "Liu, Jinsong" To: Jan Kiszka Thread-Topic: [PATCH 2/2] Expose tsc deadline timer cpuid to guest Thread-Index: AQHM9XPWlr1WsloPQ2SIOQD6lXGLW5ZSGDAg Date: Tue, 28 Feb 2012 10:30:56 +0000 Message-ID: References: <4F0482D6.8080705@web.de> <4F060961.9050002@web.de> <4F0A099C.5040805@web.de> <4F4BBAEC.2040603@siemens.com> In-Reply-To: <4F4BBAEC.2040603@siemens.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 143.182.124.21 Cc: "qemu-devel@nongnu.org" , Marcelo Tosatti , Avi Kivity , kvm , Alexey Zaytsev Subject: Re: [Qemu-devel] [PATCH 2/2] Expose tsc deadline timer cpuid to guest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org > > My point is that > > qemu-version-A [-cpu whatever] > > should provide the same VM as > > qemu-version-B -machine pc-A [-cpu whatever] > > specifically if you leave out the cpu specification. > > So the compat machine could establish a feature mask (e.g. append some > "-tsc_deadline" in this case). But, indeed, we need a new channel for > this. > Yes, if such requirement need to be satisfied, I agree we need a new channel to solve this kind of common issue. As for tsc deadline timer feature exposing, I write an updated patch as attached. 1). It exposes tsc deadline timer feature to guest if in-kernel irqchip is used and kvm has emulated tsc deadline timer; 2). It also authorizes user to control the feature exposing via a cpu feature flag; Thanks, Jinsong ==================== From 5b7d5f459b621686e78e437010ce34748bcb9e8e Mon Sep 17 00:00:00 2001 From: Liu, Jinsong Date: Wed, 29 Feb 2012 01:53:15 +0800 Subject: [PATCH] Expose tsc deadline timer feature to guest It exposes tsc deadline timer feature to guest if in-kernel irqchip is used and kvm has emulated tsc deadline timer. It also authorizes user to control the feature exposing via a cpu feature flag. Signed-off-by: Liu, Jinsong --- target-i386/cpu.h | 1 + target-i386/cpuid.c | 2 +- target-i386/kvm.c | 4 ++++ 3 files changed, 6 insertions(+), 1 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index d92be5d..3409afe 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -399,6 +399,7 @@ #define CPUID_EXT_X2APIC (1 << 21) #define CPUID_EXT_MOVBE (1 << 22) #define CPUID_EXT_POPCNT (1 << 23) +#define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) #define CPUID_EXT_XSAVE (1 << 26) #define CPUID_EXT_OSXSAVE (1 << 27) #define CPUID_EXT_HYPERVISOR (1 << 31) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index b9bfeaf..ac4b79c 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -50,7 +50,7 @@ static const char *ext_feature_name[] = { "fma", "cx16", "xtpr", "pdcm", NULL, NULL, "dca", "sse4.1|sse4_1", "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", - NULL, "aes", "xsave", "osxsave", + "tsc_deadline", "aes", "xsave", "osxsave", "avx", NULL, NULL, "hypervisor", }; static const char *ext2_feature_name[] = { diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 7079e87..2639699 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -370,6 +370,10 @@ int kvm_arch_init_vcpu(CPUState *env) i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); env->cpuid_ext_features |= i; + if (!kvm_irqchip_in_kernel() || + !kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { + env->cpuid_ext_features &= ~CPUID_EXT_TSC_DEADLINE_TIMER; + } env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);