From patchwork Mon Dec 2 16:45:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 295961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 185522C0099 for ; Tue, 3 Dec 2013 03:46:34 +1100 (EST) Received: from localhost ([::1]:37702 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnWdj-0007jD-JT for incoming@patchwork.ozlabs.org; Mon, 02 Dec 2013 11:46:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39898) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnWdJ-0007bf-LM for qemu-devel@nongnu.org; Mon, 02 Dec 2013 11:46:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VnWdE-0003oT-E7 for qemu-devel@nongnu.org; Mon, 02 Dec 2013 11:46:05 -0500 Received: from mga01.intel.com ([192.55.52.88]:50582) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnWdE-0003oC-2a for qemu-devel@nongnu.org; Mon, 02 Dec 2013 11:46:00 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 02 Dec 2013 08:45:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,811,1378882800"; d="scan'208,223";a="443261867" Received: from fmsmsx105.amr.corp.intel.com ([10.19.9.36]) by fmsmga002.fm.intel.com with ESMTP; 02 Dec 2013 08:45:22 -0800 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX105.amr.corp.intel.com (10.19.9.36) with Microsoft SMTP Server (TLS) id 14.3.123.3; Mon, 2 Dec 2013 08:45:22 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.123.3; Mon, 2 Dec 2013 08:45:21 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.57]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.235]) with mapi id 14.03.0123.003; Tue, 3 Dec 2013 00:45:19 +0800 From: "Liu, Jinsong" To: Paolo Bonzini , Gleb Natapov , "qemu-devel@nongnu.org" , kvm Thread-Topic: [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug Thread-Index: Ac7vfeIxiSbCLvRRSyiwVtbCzagqXA== Date: Mon, 2 Dec 2013 16:45:18 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.88 Cc: "haoxudong.hao@gmail.com" Subject: [Qemu-devel] [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From 4a2eb0a8467b4f278e59d2df209a1bc03349d088 Mon Sep 17 00:00:00 2001 From: Liu Jinsong Date: Tue, 3 Dec 2013 06:28:20 +0800 Subject: [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable. Bit 63 of XCR0 is reserved for future expansion. Signed-off-by: Liu Jinsong --- arch/x86/include/asm/xsave.h | 2 ++ arch/x86/kvm/cpuid.c | 6 +++--- arch/x86/kvm/x86.c | 7 +++++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h index d3e3ea5..6120e74 100644 --- a/arch/x86/include/asm/xsave.h +++ b/arch/x86/include/asm/xsave.h @@ -13,6 +13,8 @@ #define XSTATE_BNDCSR 0x10 #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE) +/* Bit 63 of XCR0 is reserved for future expansion */ +#define XSTATE_EXTEND_MASK (~(XSTATE_FPSSE | (1 << 63))) #define FXSAVE_SIZE 512 diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index c697625..2d661e6 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -28,7 +28,7 @@ static u32 xstate_required_size(u64 xstate_bv) int feature_bit = 0; u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; - xstate_bv &= ~XSTATE_FPSSE; + xstate_bv &= XSTATE_EXTEND_MASK; while (xstate_bv) { if (xstate_bv & 0x1) { u32 eax, ebx, ecx, edx; @@ -74,8 +74,8 @@ void kvm_update_cpuid(struct kvm_vcpu *vcpu) vcpu->arch.guest_supported_xcr0 = (best->eax | ((u64)best->edx << 32)) & host_xcr0 & KVM_SUPPORTED_XCR0; - vcpu->arch.guest_xstate_size = - xstate_required_size(vcpu->arch.guest_supported_xcr0); + vcpu->arch.guest_xstate_size = best->ebx = + xstate_required_size(vcpu->arch.xcr0); } kvm_pmu_cpuid_update(vcpu); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 21ef1ba..1657ca2 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -576,13 +576,13 @@ static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) { - u64 xcr0; + u64 xcr0 = xcr; + u64 old_xcr0 = vcpu->arch.xcr0; u64 valid_bits; /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ if (index != XCR_XFEATURE_ENABLED_MASK) return 1; - xcr0 = xcr; if (!(xcr0 & XSTATE_FP)) return 1; if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) @@ -599,6 +599,9 @@ int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) kvm_put_guest_xcr0(vcpu); vcpu->arch.xcr0 = xcr0; + + if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) + kvm_update_cpuid(vcpu); return 0; }