From patchwork Fri Nov 29 13:41:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 295321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 521D72C00E4 for ; Sat, 30 Nov 2013 00:42:25 +1100 (EST) Received: from localhost ([::1]:47386 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmOKq-00074n-QK for incoming@patchwork.ozlabs.org; Fri, 29 Nov 2013 08:42:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39188) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmOKU-00073g-9x for qemu-devel@nongnu.org; Fri, 29 Nov 2013 08:42:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmOKO-0005RO-OY for qemu-devel@nongnu.org; Fri, 29 Nov 2013 08:41:58 -0500 Received: from mga02.intel.com ([134.134.136.20]:12436) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmOKO-0005Qz-CA for qemu-devel@nongnu.org; Fri, 29 Nov 2013 08:41:52 -0500 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 29 Nov 2013 05:41:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,798,1378882800"; d="scan'208,223";a="444141923" Received: from fmsmsx105.amr.corp.intel.com ([10.19.9.36]) by orsmga002.jf.intel.com with ESMTP; 29 Nov 2013 05:41:51 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX105.amr.corp.intel.com (10.19.9.36) with Microsoft SMTP Server (TLS) id 14.3.123.3; Fri, 29 Nov 2013 05:41:50 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.123.3; Fri, 29 Nov 2013 05:41:50 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.57]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.86]) with mapi id 14.03.0123.003; Fri, 29 Nov 2013 21:41:48 +0800 From: "Liu, Jinsong" To: Paolo Bonzini , Gleb Natapov , "qemu-devel@nongnu.org" , kvm Thread-Topic: [PATCH 1/4] X86: Intel MPX definiation Thread-Index: Ac7tCLfi+TEESaxoQr2glm9DJeV++A== Date: Fri, 29 Nov 2013 13:41:48 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Cc: "haoxudong.hao@gmail.com" Subject: [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From 3a1a011100b38a275d8c95468c12c483e316bb15 Mon Sep 17 00:00:00 2001 From: Liu Jinsong Date: Fri, 29 Nov 2013 01:27:00 +0800 Subject: [PATCH 1/4] X86: Intel MPX definiation Signed-off-by: Xudong Hao Reviewed-by: Liu Jinsong --- arch/x86/include/asm/cpufeature.h | 2 ++ arch/x86/include/asm/xsave.h | 5 ++++- 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 89270b4..1b00b01 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -216,6 +216,7 @@ #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */ #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32]; #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h index 0415cda..d3e3ea5 100644 --- a/arch/x86/include/asm/xsave.h +++ b/arch/x86/include/asm/xsave.h @@ -9,6 +9,8 @@ #define XSTATE_FP 0x1 #define XSTATE_SSE 0x2 #define XSTATE_YMM 0x4 +#define XSTATE_BNDREGS 0x8 +#define XSTATE_BNDCSR 0x10 #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE) @@ -23,7 +25,8 @@ /* * These are the features that the OS can handle currently. */ -#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) +#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \ + XSTATE_BNDREGS | XSTATE_BNDCSR) #ifdef CONFIG_X86_64 #define REX_PREFIX "0x48, "