From patchwork Mon May 6 06:20:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay X-Patchwork-Id: 1931719 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=C7TYFl/O; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VXrsL1FvQz1xnT for ; Mon, 6 May 2024 16:21:40 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3rie-0002jQ-Sf; Mon, 06 May 2024 02:21:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3rib-0002is-MN; Mon, 06 May 2024 02:20:58 -0400 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s3riR-0006sC-2o; Mon, 06 May 2024 02:20:57 -0400 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-22e6b61d652so820305fac.0; Sun, 05 May 2024 23:20:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714976445; x=1715581245; darn=nongnu.org; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=l8uARPOXLgNrD5x5VbymwJHQnEgheFii2ZdPuVb1ADE=; b=C7TYFl/OUjyzRg3618PcWU17mJTcRVgNESYAk2QYRNhZ+CTEft77JPyqd6UoD3oPmu xV1niJuEUTQEV0/v5HXWz2Ec78lAgm/0Uv7YplbBDK/kMILeTDP1JVuanocc5YFKKJjM 19PDz/AKo/lRwNPnBMSy4UXZaV7We8O2jLtuuxiNVoQqxf+3EnGs3YWsYZ67zKZGc1e/ jFU7weptTbRG9O/1F/hfWBuBKaQ9IY5cWKwkgJR6+VWUG9Xc/Cwlv1lLqS0jWdaZEkoS lL6JyGqyOYALoGXJMcbtoKukOu0FEu3GBs/nM9sldksjG4o3o+0RdPeGOwECges48KPm yO+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714976445; x=1715581245; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=l8uARPOXLgNrD5x5VbymwJHQnEgheFii2ZdPuVb1ADE=; b=PuhH+enQrh72HTXTzzD8y7KKsFgu/1RuY/r8DOzylzAXCZUXjjwhOTJcAHhST+A2EF mgIXlonwHzycJaHbjq9Rx6hvEz7b4lV8JMDrZ/JvNWS4OXKtvghqOEN7UBzyoaMvS+XG De7etHwxMdMuXm6DYSNXYZ+Zj4guyT5kbU+EiOvNZL40m9ke8VmQWlryjK/ho2ErYM8A awZyoC7xRQ23PPNs31mjGxX+RJ3RAWd26qKQehDb1UOqvw9YpX861HIAERZQ7AbJRQbV /4Vdxp1XIw4pFsu7CnOIkt/ey8E5s9iOqnHRerKy/pw7XEzLHiDWuuos5+LFneb2pZQX +Zdg== X-Gm-Message-State: AOJu0YxkZLMvqB21lGWWSLTXQc84fNg8SP0Hsxp9nieS05DaRFkuPlrL K9erpya8vTRI0LRuhgig3upC6Aw/heqZECC3VeSZt6hb339PN/lsm6IHvYVL317KnH9XO5vwJlD 36qK/ytEYvZQH6GIkpmvdAnPtQyRw9zJlRbudNg== X-Google-Smtp-Source: AGHT+IGEOTJuGbhS2Bv++AQA/gD1BZPNURqFA0PIAXIvZnIpmdlmfK+SLwRTJdiPMkXT8RyF1hbP6mVxBj3AbSYj35w= X-Received: by 2002:a05:6870:b023:b0:233:b5dd:471c with SMTP id y35-20020a056870b02300b00233b5dd471cmr9815548oae.51.1714976444564; Sun, 05 May 2024 23:20:44 -0700 (PDT) MIME-Version: 1.0 From: Tanmay Date: Mon, 6 May 2024 11:50:30 +0530 Message-ID: Subject: [PATCH] Fixes: Indentation using TABs and improve formatting To: QEMU Developers Cc: qemu-arm@nongnu.org, Peter Maydell , "marcandre.lureau@redhat.com" , pbonzini@redhat.com, richard.henderson@linaro.org Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=tanmaynpatil105@gmail.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, I have added a patch inline that fixes indentation and formatting for some files as listed in https://gitlab.com/qemu-project/qemu/-/issues/373. Thanks, Tanmay From 46026574821c46804111eea6607a1b39314b7abe Mon Sep 17 00:00:00 2001 From: Tanmay Patil Date: Sat, 25 Nov 2023 00:53:54 +0530 Subject: [PATCH] Fixes: Indentation using TABs and improve formatting Resolves: https://gitlab.com/qemu-project/qemu/-/issues/373 Files changed: - hw/arm/boot.c - hw/char/omap_uart.c - hw/dma/pxa2xx_dma.c - hw/gpio/omap_gpio.c - hw/gpio/zaurus.c - hw/input/tsc2005.c - hw/input/tsc210x.c - hw/intc/omap_intc.c - hw/misc/cbus.c - hw/misc/omap_clk.c - hw/misc/omap_l4.c - hw/misc/omap_sdrc.c - hw/misc/omap_tap.c - hw/sd/omap_mmc.c - hw/sd/pxa2xx_mmci.c - hw/timer/omap_gptimer.c - hw/timer/omap_synctimer.c - hw/timer/pxa2xx_timer.c - include/hw/arm/pxa.h - include/hw/arm/sharpsl.h - include/hw/arm/soc_dma.h - tcg/arm/tcg-target.h Signed-off-by: Tanmay Patil --- hw/arm/boot.c | 8 +- hw/char/omap_uart.c | 49 +- hw/dma/pxa2xx_dma.c | 198 ++++---- hw/gpio/omap_gpio.c | 243 +++++----- hw/gpio/zaurus.c | 61 +-- hw/input/tsc2005.c | 130 ++--- hw/input/tsc210x.c | 442 +++++++++-------- hw/intc/omap_intc.c | 261 +++++----- hw/misc/cbus.c | 202 ++++---- hw/misc/omap_clk.c | 999 +++++++++++++++++++------------------- hw/misc/omap_l4.c | 21 +- hw/misc/omap_sdrc.c | 135 +++--- hw/misc/omap_tap.c | 28 +- hw/sd/omap_mmc.c | 208 ++++---- hw/sd/pxa2xx_mmci.c | 149 +++--- hw/timer/omap_gptimer.c | 126 ++--- hw/timer/omap_synctimer.c | 7 +- hw/timer/pxa2xx_timer.c | 279 ++++++----- include/hw/arm/pxa.h | 100 ++-- include/hw/arm/sharpsl.h | 2 +- include/hw/arm/soc_dma.h | 4 +- tcg/arm/tcg-target.h | 4 +- 22 files changed, 1903 insertions(+), 1753 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 84ea6a807a..d480a7da02 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -347,13 +347,13 @@ static void set_kernel_args_old(const struct arm_boot_info *info, WRITE_WORD(p, info->ram_size / 4096); /* ramdisk_size */ WRITE_WORD(p, 0); -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 +#define FLAG_READONLY 1 +#define FLAG_RDLOAD 4 +#define FLAG_RDPROMPT 8 /* flags */ WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); /* rootdev */ - WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ + WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ /* video_num_cols */ WRITE_WORD(p, 0); /* video_num_rows */ diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c index 6848bddb4e..c2ef4c137e 100644 --- a/hw/char/omap_uart.c +++ b/hw/char/omap_uart.c @@ -61,7 +61,7 @@ struct omap_uart_s *omap_uart_init(hwaddr base, s->fclk = fclk; s->irq = irq; s->serial = serial_mm_init(get_system_memory(), base, 2, irq, - omap_clk_getrate(fclk)/16, + omap_clk_getrate(fclk) / 16, chr ?: qemu_chr_new(label, "null", NULL), DEVICE_NATIVE_ENDIAN); return s; @@ -76,27 +76,27 @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size) } switch (addr) { - case 0x20: /* MDR1 */ + case 0x20: /* MDR1 */ return s->mdr[0]; - case 0x24: /* MDR2 */ + case 0x24: /* MDR2 */ return s->mdr[1]; - case 0x40: /* SCR */ + case 0x40: /* SCR */ return s->scr; - case 0x44: /* SSR */ + case 0x44: /* SSR */ return 0x0; - case 0x48: /* EBLR (OMAP2) */ + case 0x48: /* EBLR (OMAP2) */ return s->eblr; - case 0x4C: /* OSC_12M_SEL (OMAP1) */ + case 0x4C: /* OSC_12M_SEL (OMAP1) */ return s->clksel; - case 0x50: /* MVR */ + case 0x50: /* MVR */ return 0x30; - case 0x54: /* SYSC (OMAP2) */ + case 0x54: /* SYSC (OMAP2) */ return s->syscontrol; - case 0x58: /* SYSS (OMAP2) */ + case 0x58: /* SYSS (OMAP2) */ return 1; - case 0x5c: /* WER (OMAP2) */ + case 0x5c: /* WER (OMAP2) */ return s->wkup; - case 0x60: /* CFPS (OMAP2) */ + case 0x60: /* CFPS (OMAP2) */ return s->cfps; } @@ -115,35 +115,36 @@ static void omap_uart_write(void *opaque, hwaddr addr, } switch (addr) { - case 0x20: /* MDR1 */ + case 0x20: /* MDR1 */ s->mdr[0] = value & 0x7f; break; - case 0x24: /* MDR2 */ + case 0x24: /* MDR2 */ s->mdr[1] = value & 0xff; break; - case 0x40: /* SCR */ + case 0x40: /* SCR */ s->scr = value & 0xff; break; - case 0x48: /* EBLR (OMAP2) */ + case 0x48: /* EBLR (OMAP2) */ s->eblr = value & 0xff; break; - case 0x4C: /* OSC_12M_SEL (OMAP1) */ + case 0x4C: /* OSC_12M_SEL (OMAP1) */ s->clksel = value & 1; break; - case 0x44: /* SSR */ - case 0x50: /* MVR */ - case 0x58: /* SYSS (OMAP2) */ + case 0x44: /* SSR */ + case 0x50: /* MVR */ + case 0x58: /* SYSS (OMAP2) */ OMAP_RO_REG(addr); break; - case 0x54: /* SYSC (OMAP2) */ + case 0x54: /* SYSC (OMAP2) */ s->syscontrol = value & 0x1d; - if (value & 2) + if (value & 2) { omap_uart_reset(s); + } break; - case 0x5c: /* WER (OMAP2) */ + case 0x5c: /* WER (OMAP2) */ s->wkup = value & 0x7f; break; - case 0x60: /* CFPS (OMAP2) */ + case 0x60: /* CFPS (OMAP2) */ s->cfps = value & 0xff; break; default: diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c index 9f62f0b633..beed1cd9a5 100644 --- a/hw/dma/pxa2xx_dma.c +++ b/hw/dma/pxa2xx_dma.c @@ -61,98 +61,104 @@ struct PXA2xxDMAState { int running; }; -#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ -#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ -#define DALGN 0x00a0 /* DMA Alignment register */ -#define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */ -#define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */ -#define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */ -#define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */ -#define DINT 0x00f0 /* DMA Interrupt register */ -#define DRCMR0 0x0100 /* Request to Channel Map register 0 */ -#define DRCMR63 0x01fc /* Request to Channel Map register 63 */ -#define D_CH0 0x0200 /* Channel 0 Descriptor start */ -#define DRCMR64 0x1100 /* Request to Channel Map register 64 */ -#define DRCMR74 0x1128 /* Request to Channel Map register 74 */ +#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ +#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ +#define DALGN 0x00a0 /* DMA Alignment register */ +#define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */ +#define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */ +#define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */ +#define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */ +#define DINT 0x00f0 /* DMA Interrupt register */ +#define DRCMR0 0x0100 /* Request to Channel Map register 0 */ +#define DRCMR63 0x01fc /* Request to Channel Map register 63 */ +#define D_CH0 0x0200 /* Channel 0 Descriptor start */ +#define DRCMR64 0x1100 /* Request to Channel Map register 64 */ +#define DRCMR74 0x1128 /* Request to Channel Map register 74 */ /* Per-channel register */ -#define DDADR 0x00 -#define DSADR 0x01 -#define DTADR 0x02 -#define DCMD 0x03 +#define DDADR 0x00 +#define DSADR 0x01 +#define DTADR 0x02 +#define DCMD 0x03 /* Bit-field masks */ -#define DRCMR_CHLNUM 0x1f -#define DRCMR_MAPVLD (1 << 7) -#define DDADR_STOP (1 << 0) -#define DDADR_BREN (1 << 1) -#define DCMD_LEN 0x1fff -#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1)) -#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3)) -#define DCMD_FLYBYT (1 << 19) -#define DCMD_FLYBYS (1 << 20) -#define DCMD_ENDIRQEN (1 << 21) -#define DCMD_STARTIRQEN (1 << 22) -#define DCMD_CMPEN (1 << 25) -#define DCMD_FLOWTRG (1 << 28) -#define DCMD_FLOWSRC (1 << 29) -#define DCMD_INCTRGADDR (1 << 30) -#define DCMD_INCSRCADDR (1 << 31) -#define DCSR_BUSERRINTR (1 << 0) -#define DCSR_STARTINTR (1 << 1) -#define DCSR_ENDINTR (1 << 2) -#define DCSR_STOPINTR (1 << 3) -#define DCSR_RASINTR (1 << 4) -#define DCSR_REQPEND (1 << 8) -#define DCSR_EORINT (1 << 9) -#define DCSR_CMPST (1 << 10) -#define DCSR_MASKRUN (1 << 22) -#define DCSR_RASIRQEN (1 << 23) -#define DCSR_CLRCMPST (1 << 24) -#define DCSR_SETCMPST (1 << 25) -#define DCSR_EORSTOPEN (1 << 26) -#define DCSR_EORJMPEN (1 << 27) -#define DCSR_EORIRQEN (1 << 28) -#define DCSR_STOPIRQEN (1 << 29) -#define DCSR_NODESCFETCH (1 << 30) -#define DCSR_RUN (1 << 31) +#define DRCMR_CHLNUM 0x1f +#define DRCMR_MAPVLD (1 << 7) +#define DDADR_STOP (1 << 0) +#define DDADR_BREN (1 << 1) +#define DCMD_LEN 0x1fff +#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1)) +#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3)) +#define DCMD_FLYBYT (1 << 19) +#define DCMD_FLYBYS (1 << 20) +#define DCMD_ENDIRQEN (1 << 21) +#define DCMD_STARTIRQEN (1 << 22) +#define DCMD_CMPEN (1 << 25) +#define DCMD_FLOWTRG (1 << 28) +#define DCMD_FLOWSRC (1 << 29) +#define DCMD_INCTRGADDR (1 << 30) +#define DCMD_INCSRCADDR (1 << 31) +#define DCSR_BUSERRINTR (1 << 0) +#define DCSR_STARTINTR (1 << 1) +#define DCSR_ENDINTR (1 << 2) +#define DCSR_STOPINTR (1 << 3) +#define DCSR_RASINTR (1 << 4) +#define DCSR_REQPEND (1 << 8) +#define DCSR_EORINT (1 << 9) +#define DCSR_CMPST (1 << 10) +#define DCSR_MASKRUN (1 << 22) +#define DCSR_RASIRQEN (1 << 23) +#define DCSR_CLRCMPST (1 << 24) +#define DCSR_SETCMPST (1 << 25) +#define DCSR_EORSTOPEN (1 << 26) +#define DCSR_EORJMPEN (1 << 27) +#define DCSR_EORIRQEN (1 << 28) +#define DCSR_STOPIRQEN (1 << 29) +#define DCSR_NODESCFETCH (1 << 30) +#define DCSR_RUN (1 << 31) static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch) { if (ch >= 0) { if ((s->chan[ch].state & DCSR_STOPIRQEN) && - (s->chan[ch].state & DCSR_STOPINTR)) + (s->chan[ch].state & DCSR_STOPINTR)) { s->stopintr |= 1 << ch; - else + } else { s->stopintr &= ~(1 << ch); + } if ((s->chan[ch].state & DCSR_EORIRQEN) && - (s->chan[ch].state & DCSR_EORINT)) + (s->chan[ch].state & DCSR_EORINT)) { s->eorintr |= 1 << ch; - else + } else { s->eorintr &= ~(1 << ch); + } if ((s->chan[ch].state & DCSR_RASIRQEN) && - (s->chan[ch].state & DCSR_RASINTR)) + (s->chan[ch].state & DCSR_RASINTR)) { s->rasintr |= 1 << ch; - else + } else { s->rasintr &= ~(1 << ch); + } - if (s->chan[ch].state & DCSR_STARTINTR) + if (s->chan[ch].state & DCSR_STARTINTR) { s->startintr |= 1 << ch; - else + } else { s->startintr &= ~(1 << ch); + } - if (s->chan[ch].state & DCSR_ENDINTR) + if (s->chan[ch].state & DCSR_ENDINTR) { s->endintr |= 1 << ch; - else + } else { s->endintr &= ~(1 << ch); + } } - if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr) + if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr) { qemu_irq_raise(s->irq); - else + } else { qemu_irq_lower(s->irq); + } } static inline void pxa2xx_dma_descriptor_fetch( @@ -160,8 +166,9 @@ static inline void pxa2xx_dma_descriptor_fetch( { uint32_t desc[4]; hwaddr daddr = s->chan[ch].descr & ~0xf; - if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST)) + if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST)) { daddr += 32; + } cpu_physical_memory_read(daddr, desc, 16); s->chan[ch].descr = desc[DDADR]; @@ -169,16 +176,20 @@ static inline void pxa2xx_dma_descriptor_fetch( s->chan[ch].dest = desc[DTADR]; s->chan[ch].cmd = desc[DCMD]; - if (s->chan[ch].cmd & DCMD_FLOWSRC) + if (s->chan[ch].cmd & DCMD_FLOWSRC) { s->chan[ch].src &= ~3; - if (s->chan[ch].cmd & DCMD_FLOWTRG) + } + if (s->chan[ch].cmd & DCMD_FLOWTRG) { s->chan[ch].dest &= ~3; + } - if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT)) + if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT)) { printf("%s: unsupported mode in channel %i\n", __func__, ch); + } - if (s->chan[ch].cmd & DCMD_STARTIRQEN) + if (s->chan[ch].cmd & DCMD_STARTIRQEN) { s->chan[ch].state |= DCSR_STARTINTR; + } } static void pxa2xx_dma_run(PXA2xxDMAState *s) @@ -190,18 +201,20 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s) uint8_t buffer[32]; PXA2xxDMAChannel *ch; - if (s->running ++) + if (s->running++) { return; + } while (s->running) { s->running = 1; - for (c = 0; c < s->channels; c ++) { + for (c = 0; c < s->channels; c++) { ch = &s->chan[c]; while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) { /* Test for pending requests */ - if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) + if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) { break; + } length = ch->cmd & DCMD_LEN; size = DCMD_SIZE(ch->cmd); @@ -228,11 +241,13 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s) if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) { ch->state |= DCSR_EORINT; - if (ch->state & DCSR_EORSTOPEN) + if (ch->state & DCSR_EORSTOPEN) { ch->state |= DCSR_STOPINTR; + } if ((ch->state & DCSR_EORJMPEN) && - !(ch->state & DCSR_NODESCFETCH)) + !(ch->state & DCSR_NODESCFETCH)) { pxa2xx_dma_descriptor_fetch(s, c); + } break; } } @@ -241,8 +256,9 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s) /* Is the transfer complete now? */ if (!length) { - if (ch->cmd & DCMD_ENDIRQEN) + if (ch->cmd & DCMD_ENDIRQEN) { ch->state |= DCSR_ENDINTR; + } if ((ch->state & DCSR_NODESCFETCH) || (ch->descr & DDADR_STOP) || @@ -259,7 +275,7 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s) } } - s->running --; + s->running--; } } @@ -290,8 +306,9 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset, case DCSR0 ... DCSR31: channel = offset >> 2; - if (s->chan[channel].request) + if (s->chan[channel].request) { return s->chan[channel].state | DCSR_REQPEND; + } return s->chan[channel].state; case DINT: @@ -363,8 +380,9 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset, DCSR_STARTINTR | DCSR_BUSERRINTR)); s->chan[channel].state |= value & 0xfc800000; - if (s->chan[channel].state & DCSR_STOPIRQEN) + if (s->chan[channel].state & DCSR_STOPIRQEN) { s->chan[channel].state &= ~DCSR_STOPINTR; + } if (value & DCSR_NODESCFETCH) { /* No-descriptor-fetch mode */ @@ -382,13 +400,16 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset, } /* Shouldn't matter as our DMA is synchronous. */ - if (!(value & (DCSR_RUN | DCSR_MASKRUN))) + if (!(value & (DCSR_RUN | DCSR_MASKRUN))) { s->chan[channel].state |= DCSR_STOPINTR; + } - if (value & DCSR_CLRCMPST) + if (value & DCSR_CLRCMPST) { s->chan[channel].state &= ~DCSR_CMPST; - if (value & DCSR_SETCMPST) + } + if (value & DCSR_SETCMPST) { s->chan[channel].state |= DCSR_CMPST; + } pxa2xx_dma_update(s, channel); break; @@ -439,19 +460,23 @@ static void pxa2xx_dma_request(void *opaque, int req_num, int on) { PXA2xxDMAState *s = opaque; int ch; - if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) + if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) { hw_error("%s: Bad DMA request %i\n", __func__, req_num); + } - if (!(s->req[req_num] & DRCMR_MAPVLD)) + if (!(s->req[req_num] & DRCMR_MAPVLD)) { return; + } ch = s->req[req_num] & DRCMR_CHLNUM; - if (!s->chan[ch].request && on) + if (!s->chan[ch].request && on) { s->chan[ch].state |= DCSR_RASINTR; - else + } else { s->chan[ch].state &= ~DCSR_RASINTR; - if (s->chan[ch].request && !on) + } + if (s->chan[ch].request && !on) { s->chan[ch].state |= DCSR_EORINT; + } s->chan[ch].request = on; if (on) { @@ -488,8 +513,9 @@ static void pxa2xx_dma_realize(DeviceState *dev, Error **errp) s->chan = g_new0(PXA2xxDMAChannel, s->channels); - for (i = 0; i < s->channels; i ++) + for (i = 0; i < s->channels; i++) { s->chan[i].state = DCSR_STOPINTR; + } } DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq) diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index a3341d70f1..60e97a0839 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -57,10 +57,11 @@ static void omap_gpio_set(void *opaque, int line, int level) struct omap_gpio_s *s = &p->omap1; uint16_t prev = s->inputs; - if (level) + if (level) { s->inputs |= 1 << line; - else + } else { s->inputs &= ~(1 << line); + } if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & (1 << line) & s->dir & ~s->mask) { @@ -80,25 +81,25 @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr, } switch (offset) { - case 0x00: /* DATA_INPUT */ + case 0x00: /* DATA_INPUT */ return s->inputs & s->pins; - case 0x04: /* DATA_OUTPUT */ + case 0x04: /* DATA_OUTPUT */ return s->outputs; - case 0x08: /* DIRECTION_CONTROL */ + case 0x08: /* DIRECTION_CONTROL */ return s->dir; - case 0x0c: /* INTERRUPT_CONTROL */ + case 0x0c: /* INTERRUPT_CONTROL */ return s->edge; - case 0x10: /* INTERRUPT_MASK */ + case 0x10: /* INTERRUPT_MASK */ return s->mask; - case 0x14: /* INTERRUPT_STATUS */ + case 0x14: /* INTERRUPT_STATUS */ return s->ints; - case 0x18: /* PIN_CONTROL (not in OMAP310) */ + case 0x18: /* PIN_CONTROL (not in OMAP310) */ OMAP_BAD_REG(addr); return s->pins; } @@ -121,47 +122,50 @@ static void omap_gpio_write(void *opaque, hwaddr addr, } switch (offset) { - case 0x00: /* DATA_INPUT */ + case 0x00: /* DATA_INPUT */ OMAP_RO_REG(addr); return; - case 0x04: /* DATA_OUTPUT */ + case 0x04: /* DATA_OUTPUT */ diff = (s->outputs ^ value) & ~s->dir; s->outputs = value; while ((ln = ctz32(diff)) != 32) { - if (s->handler[ln]) + if (s->handler[ln]) { qemu_set_irq(s->handler[ln], (value >> ln) & 1); + } diff &= ~(1 << ln); } break; - case 0x08: /* DIRECTION_CONTROL */ + case 0x08: /* DIRECTION_CONTROL */ diff = s->outputs & (s->dir ^ value); s->dir = value; value = s->outputs & ~s->dir; while ((ln = ctz32(diff)) != 32) { - if (s->handler[ln]) + if (s->handler[ln]) { qemu_set_irq(s->handler[ln], (value >> ln) & 1); + } diff &= ~(1 << ln); } break; - case 0x0c: /* INTERRUPT_CONTROL */ + case 0x0c: /* INTERRUPT_CONTROL */ s->edge = value; break; - case 0x10: /* INTERRUPT_MASK */ + case 0x10: /* INTERRUPT_MASK */ s->mask = value; break; - case 0x14: /* INTERRUPT_STATUS */ + case 0x14: /* INTERRUPT_STATUS */ s->ints &= ~value; - if (!s->ints) + if (!s->ints) { qemu_irq_lower(s->irq); + } break; - case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ + case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ OMAP_BAD_REG(addr); s->pins = value; break; @@ -233,12 +237,15 @@ static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s, static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line) { - if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ + if (!(s->config[0] & (1 << 2))) { /* ENAWAKEUP */ return; - if (!(s->config[0] & (3 << 3))) /* Force Idle */ + } + if (!(s->config[0] & (3 << 3))) { /* Force Idle */ return; - if (!(s->wumask & (1 << line))) + } + if (!(s->wumask & (1 << line))) { return; + } qemu_irq_raise(s->wkup); } @@ -279,12 +286,14 @@ static void omap2_gpio_set(void *opaque, int line, int level) line &= 31; if (level) { - if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) + if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) { omap2_gpio_module_int(s, line); + } s->inputs |= 1 << line; } else { - if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) + if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) { omap2_gpio_module_int(s, line); + } s->inputs &= ~(1 << line); } } @@ -312,66 +321,66 @@ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr) struct omap2_gpio_s *s = opaque; switch (addr) { - case 0x00: /* GPIO_REVISION */ + case 0x00: /* GPIO_REVISION */ return s->revision; - case 0x10: /* GPIO_SYSCONFIG */ + case 0x10: /* GPIO_SYSCONFIG */ return s->config[0]; - case 0x14: /* GPIO_SYSSTATUS */ + case 0x14: /* GPIO_SYSSTATUS */ return 0x01; - case 0x18: /* GPIO_IRQSTATUS1 */ + case 0x18: /* GPIO_IRQSTATUS1 */ return s->ints[0]; - case 0x1c: /* GPIO_IRQENABLE1 */ - case 0x60: /* GPIO_CLEARIRQENABLE1 */ - case 0x64: /* GPIO_SETIRQENABLE1 */ + case 0x1c: /* GPIO_IRQENABLE1 */ + case 0x60: /* GPIO_CLEARIRQENABLE1 */ + case 0x64: /* GPIO_SETIRQENABLE1 */ return s->mask[0]; - case 0x20: /* GPIO_WAKEUPENABLE */ - case 0x80: /* GPIO_CLEARWKUENA */ - case 0x84: /* GPIO_SETWKUENA */ + case 0x20: /* GPIO_WAKEUPENABLE */ + case 0x80: /* GPIO_CLEARWKUENA */ + case 0x84: /* GPIO_SETWKUENA */ return s->wumask; - case 0x28: /* GPIO_IRQSTATUS2 */ + case 0x28: /* GPIO_IRQSTATUS2 */ return s->ints[1]; - case 0x2c: /* GPIO_IRQENABLE2 */ - case 0x70: /* GPIO_CLEARIRQENABLE2 */ - case 0x74: /* GPIO_SETIREQNEABLE2 */ + case 0x2c: /* GPIO_IRQENABLE2 */ + case 0x70: /* GPIO_CLEARIRQENABLE2 */ + case 0x74: /* GPIO_SETIREQNEABLE2 */ return s->mask[1]; - case 0x30: /* GPIO_CTRL */ + case 0x30: /* GPIO_CTRL */ return s->config[1]; - case 0x34: /* GPIO_OE */ + case 0x34: /* GPIO_OE */ return s->dir; - case 0x38: /* GPIO_DATAIN */ + case 0x38: /* GPIO_DATAIN */ return s->inputs; - case 0x3c: /* GPIO_DATAOUT */ - case 0x90: /* GPIO_CLEARDATAOUT */ - case 0x94: /* GPIO_SETDATAOUT */ + case 0x3c: /* GPIO_DATAOUT */ + case 0x90: /* GPIO_CLEARDATAOUT */ + case 0x94: /* GPIO_SETDATAOUT */ return s->outputs; - case 0x40: /* GPIO_LEVELDETECT0 */ + case 0x40: /* GPIO_LEVELDETECT0 */ return s->level[0]; - case 0x44: /* GPIO_LEVELDETECT1 */ + case 0x44: /* GPIO_LEVELDETECT1 */ return s->level[1]; - case 0x48: /* GPIO_RISINGDETECT */ + case 0x48: /* GPIO_RISINGDETECT */ return s->edge[0]; - case 0x4c: /* GPIO_FALLINGDETECT */ + case 0x4c: /* GPIO_FALLINGDETECT */ return s->edge[1]; - case 0x50: /* GPIO_DEBOUNCENABLE */ + case 0x50: /* GPIO_DEBOUNCENABLE */ return s->debounce; - case 0x54: /* GPIO_DEBOUNCINGTIME */ + case 0x54: /* GPIO_DEBOUNCINGTIME */ return s->delay; } @@ -387,55 +396,56 @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr, int ln; switch (addr) { - case 0x00: /* GPIO_REVISION */ - case 0x14: /* GPIO_SYSSTATUS */ - case 0x38: /* GPIO_DATAIN */ + case 0x00: /* GPIO_REVISION */ + case 0x14: /* GPIO_SYSSTATUS */ + case 0x38: /* GPIO_DATAIN */ OMAP_RO_REG(addr); break; - case 0x10: /* GPIO_SYSCONFIG */ + case 0x10: /* GPIO_SYSCONFIG */ if (((value >> 3) & 3) == 3) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Illegal IDLEMODE value: 3\n", __func__); } - if (value & 2) + if (value & 2) { omap2_gpio_module_reset(s); + } s->config[0] = value & 0x1d; break; - case 0x18: /* GPIO_IRQSTATUS1 */ + case 0x18: /* GPIO_IRQSTATUS1 */ if (s->ints[0] & value) { s->ints[0] &= ~value; omap2_gpio_module_level_update(s, 0); } break; - case 0x1c: /* GPIO_IRQENABLE1 */ + case 0x1c: /* GPIO_IRQENABLE1 */ s->mask[0] = value; omap2_gpio_module_int_update(s, 0); break; - case 0x20: /* GPIO_WAKEUPENABLE */ + case 0x20: /* GPIO_WAKEUPENABLE */ s->wumask = value; break; - case 0x28: /* GPIO_IRQSTATUS2 */ + case 0x28: /* GPIO_IRQSTATUS2 */ if (s->ints[1] & value) { s->ints[1] &= ~value; omap2_gpio_module_level_update(s, 1); } break; - case 0x2c: /* GPIO_IRQENABLE2 */ + case 0x2c: /* GPIO_IRQENABLE2 */ s->mask[1] = value; omap2_gpio_module_int_update(s, 1); break; - case 0x30: /* GPIO_CTRL */ + case 0x30: /* GPIO_CTRL */ s->config[1] = value & 7; break; - case 0x34: /* GPIO_OE */ + case 0x34: /* GPIO_OE */ diff = s->outputs & (s->dir ^ value); s->dir = value; @@ -449,71 +459,71 @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr, omap2_gpio_module_level_update(s, 1); break; - case 0x3c: /* GPIO_DATAOUT */ + case 0x3c: /* GPIO_DATAOUT */ omap2_gpio_module_out_update(s, s->outputs ^ value); break; - case 0x40: /* GPIO_LEVELDETECT0 */ + case 0x40: /* GPIO_LEVELDETECT0 */ s->level[0] = value; omap2_gpio_module_level_update(s, 0); omap2_gpio_module_level_update(s, 1); break; - case 0x44: /* GPIO_LEVELDETECT1 */ + case 0x44: /* GPIO_LEVELDETECT1 */ s->level[1] = value; omap2_gpio_module_level_update(s, 0); omap2_gpio_module_level_update(s, 1); break; - case 0x48: /* GPIO_RISINGDETECT */ + case 0x48: /* GPIO_RISINGDETECT */ s->edge[0] = value; break; - case 0x4c: /* GPIO_FALLINGDETECT */ + case 0x4c: /* GPIO_FALLINGDETECT */ s->edge[1] = value; break; - case 0x50: /* GPIO_DEBOUNCENABLE */ + case 0x50: /* GPIO_DEBOUNCENABLE */ s->debounce = value; break; - case 0x54: /* GPIO_DEBOUNCINGTIME */ + case 0x54: /* GPIO_DEBOUNCINGTIME */ s->delay = value; break; - case 0x60: /* GPIO_CLEARIRQENABLE1 */ + case 0x60: /* GPIO_CLEARIRQENABLE1 */ s->mask[0] &= ~value; omap2_gpio_module_int_update(s, 0); break; - case 0x64: /* GPIO_SETIRQENABLE1 */ + case 0x64: /* GPIO_SETIRQENABLE1 */ s->mask[0] |= value; omap2_gpio_module_int_update(s, 0); break; - case 0x70: /* GPIO_CLEARIRQENABLE2 */ + case 0x70: /* GPIO_CLEARIRQENABLE2 */ s->mask[1] &= ~value; omap2_gpio_module_int_update(s, 1); break; - case 0x74: /* GPIO_SETIREQNEABLE2 */ + case 0x74: /* GPIO_SETIREQNEABLE2 */ s->mask[1] |= value; omap2_gpio_module_int_update(s, 1); break; - case 0x80: /* GPIO_CLEARWKUENA */ + case 0x80: /* GPIO_CLEARWKUENA */ s->wumask &= ~value; break; - case 0x84: /* GPIO_SETWKUENA */ + case 0x84: /* GPIO_SETWKUENA */ s->wumask |= value; break; - case 0x90: /* GPIO_CLEARDATAOUT */ + case 0x90: /* GPIO_CLEARDATAOUT */ omap2_gpio_module_out_update(s, s->outputs & value); break; - case 0x94: /* GPIO_SETDATAOUT */ + case 0x94: /* GPIO_SETDATAOUT */ omap2_gpio_module_out_update(s, ~s->outputs & value); break; @@ -541,39 +551,39 @@ static void omap2_gpio_module_writep(void *opaque, hwaddr addr, } switch (addr & ~3) { - case 0x00: /* GPIO_REVISION */ - case 0x14: /* GPIO_SYSSTATUS */ - case 0x38: /* GPIO_DATAIN */ + case 0x00: /* GPIO_REVISION */ + case 0x14: /* GPIO_SYSSTATUS */ + case 0x38: /* GPIO_DATAIN */ OMAP_RO_REG(addr); break; - case 0x10: /* GPIO_SYSCONFIG */ - case 0x1c: /* GPIO_IRQENABLE1 */ - case 0x20: /* GPIO_WAKEUPENABLE */ - case 0x2c: /* GPIO_IRQENABLE2 */ - case 0x30: /* GPIO_CTRL */ - case 0x34: /* GPIO_OE */ - case 0x3c: /* GPIO_DATAOUT */ - case 0x40: /* GPIO_LEVELDETECT0 */ - case 0x44: /* GPIO_LEVELDETECT1 */ - case 0x48: /* GPIO_RISINGDETECT */ - case 0x4c: /* GPIO_FALLINGDETECT */ - case 0x50: /* GPIO_DEBOUNCENABLE */ - case 0x54: /* GPIO_DEBOUNCINGTIME */ + case 0x10: /* GPIO_SYSCONFIG */ + case 0x1c: /* GPIO_IRQENABLE1 */ + case 0x20: /* GPIO_WAKEUPENABLE */ + case 0x2c: /* GPIO_IRQENABLE2 */ + case 0x30: /* GPIO_CTRL */ + case 0x34: /* GPIO_OE */ + case 0x3c: /* GPIO_DATAOUT */ + case 0x40: /* GPIO_LEVELDETECT0 */ + case 0x44: /* GPIO_LEVELDETECT1 */ + case 0x48: /* GPIO_RISINGDETECT */ + case 0x4c: /* GPIO_FALLINGDETECT */ + case 0x50: /* GPIO_DEBOUNCENABLE */ + case 0x54: /* GPIO_DEBOUNCINGTIME */ cur = omap2_gpio_module_read(opaque, addr & ~3) & ~(mask << ((addr & 3) << 3)); /* Fall through. */ - case 0x18: /* GPIO_IRQSTATUS1 */ - case 0x28: /* GPIO_IRQSTATUS2 */ - case 0x60: /* GPIO_CLEARIRQENABLE1 */ - case 0x64: /* GPIO_SETIRQENABLE1 */ - case 0x70: /* GPIO_CLEARIRQENABLE2 */ - case 0x74: /* GPIO_SETIREQNEABLE2 */ - case 0x80: /* GPIO_CLEARWKUENA */ - case 0x84: /* GPIO_SETWKUENA */ - case 0x90: /* GPIO_CLEARDATAOUT */ - case 0x94: /* GPIO_SETDATAOUT */ + case 0x18: /* GPIO_IRQSTATUS1 */ + case 0x28: /* GPIO_IRQSTATUS2 */ + case 0x60: /* GPIO_CLEARIRQENABLE1 */ + case 0x64: /* GPIO_SETIRQENABLE1 */ + case 0x70: /* GPIO_CLEARIRQENABLE2 */ + case 0x74: /* GPIO_SETIREQNEABLE2 */ + case 0x80: /* GPIO_CLEARWKUENA */ + case 0x84: /* GPIO_SETWKUENA */ + case 0x90: /* GPIO_CLEARDATAOUT */ + case 0x94: /* GPIO_SETDATAOUT */ value <<= (addr & 3) << 3; omap2_gpio_module_write(opaque, addr, cur | value); break; @@ -616,22 +626,22 @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size) Omap2GpioState *s = opaque; switch (addr) { - case 0x00: /* IPGENERICOCPSPL_REVISION */ + case 0x00: /* IPGENERICOCPSPL_REVISION */ return 0x18; - case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ + case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ return s->autoidle; - case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ + case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ return 0x01; - case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ + case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ return 0x00; - case 0x40: /* IPGENERICOCPSPL_GPO */ + case 0x40: /* IPGENERICOCPSPL_GPO */ return s->gpo; - case 0x50: /* IPGENERICOCPSPL_GPI */ + case 0x50: /* IPGENERICOCPSPL_GPI */ return 0x00; } @@ -645,20 +655,21 @@ static void omap2_gpif_top_write(void *opaque, hwaddr addr, Omap2GpioState *s = opaque; switch (addr) { - case 0x00: /* IPGENERICOCPSPL_REVISION */ - case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ - case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ - case 0x50: /* IPGENERICOCPSPL_GPI */ + case 0x00: /* IPGENERICOCPSPL_REVISION */ + case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ + case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ + case 0x50: /* IPGENERICOCPSPL_GPI */ OMAP_RO_REG(addr); break; - case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ - if (value & (1 << 1)) /* SOFTRESET */ + case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ + if (value & (1 << 1)) { /* SOFTRESET */ omap2_gpif_reset(DEVICE(s)); + } s->autoidle = value & 1; break; - case 0x40: /* IPGENERICOCPSPL_GPO */ + case 0x40: /* IPGENERICOCPSPL_GPO */ s->gpo = value & 1; break; diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c index 5884804c58..7342440b95 100644 --- a/hw/gpio/zaurus.c +++ b/hw/gpio/zaurus.c @@ -49,19 +49,20 @@ struct ScoopInfo { uint16_t isr; }; -#define SCOOP_MCR 0x00 -#define SCOOP_CDR 0x04 -#define SCOOP_CSR 0x08 -#define SCOOP_CPR 0x0c -#define SCOOP_CCR 0x10 -#define SCOOP_IRR_IRM 0x14 -#define SCOOP_IMR 0x18 -#define SCOOP_ISR 0x1c -#define SCOOP_GPCR 0x20 -#define SCOOP_GPWR 0x24 -#define SCOOP_GPRR 0x28 - -static inline void scoop_gpio_handler_update(ScoopInfo *s) { +#define SCOOP_MCR 0x00 +#define SCOOP_CDR 0x04 +#define SCOOP_CSR 0x08 +#define SCOOP_CPR 0x0c +#define SCOOP_CCR 0x10 +#define SCOOP_IRR_IRM 0x14 +#define SCOOP_IMR 0x18 +#define SCOOP_ISR 0x1c +#define SCOOP_GPCR 0x20 +#define SCOOP_GPWR 0x24 +#define SCOOP_GPRR 0x28 + +static inline void scoop_gpio_handler_update(ScoopInfo *s) +{ uint32_t level, diff; int bit; level = s->gpio_level & s->gpio_dir; @@ -125,8 +126,9 @@ static void scoop_write(void *opaque, hwaddr addr, break; case SCOOP_CPR: s->power = value; - if (value & 0x80) + if (value & 0x80) { s->power |= 0x8040; + } break; case SCOOP_CCR: s->ccr = value; @@ -145,7 +147,7 @@ static void scoop_write(void *opaque, hwaddr addr, scoop_gpio_handler_update(s); break; case SCOOP_GPWR: - case SCOOP_GPRR: /* GPRR is probably R/O in real HW */ + case SCOOP_GPRR: /* GPRR is probably R/O in real HW */ s->gpio_level = value & s->gpio_dir; scoop_gpio_handler_update(s); break; @@ -166,10 +168,11 @@ static void scoop_gpio_set(void *opaque, int line, int level) { ScoopInfo *s = (ScoopInfo *) opaque; - if (level) + if (level) { s->gpio_level |= (1 << line); - else + } else { s->gpio_level &= ~(1 << line); + } } static void scoop_init(Object *obj) @@ -203,7 +206,7 @@ static int scoop_post_load(void *opaque, int version_id) return 0; } -static bool is_version_0 (void *opaque, int version_id) +static bool is_version_0(void *opaque, int version_id) { return version_id == 0; } @@ -265,7 +268,7 @@ type_init(scoop_register_types) /* Write the bootloader parameters memory area. */ -#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) +#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) static struct QEMU_PACKED sl_param_info { uint32_t comadj_keyword; @@ -286,16 +289,16 @@ static struct QEMU_PACKED sl_param_info { uint32_t phad_keyword; int32_t phadadj; } zaurus_bootparam = { - .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), - .comadj = 125, - .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), - .uuid = { -1 }, - .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), - .touch_xp = -1, - .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), - .adadj = -1, - .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), - .phadadj = 0x01, + .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), + .comadj = 125, + .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), + .uuid = { -1 }, + .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), + .touch_xp = -1, + .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), + .adadj = -1, + .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), + .phadadj = 0x01, }; void sl_bootparam_write(hwaddr ptr) diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c index 941f163d36..05094ab2b1 100644 --- a/hw/input/tsc2005.c +++ b/hw/input/tsc2005.c @@ -28,10 +28,10 @@ #include "migration/vmstate.h" #include "trace.h" -#define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - (p ? 12 : 10))) +#define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - (p ? 12 : 10))) typedef struct { - qemu_irq pint; /* Combination of the nPENIRQ and DAV signals */ + qemu_irq pint; /* Combination of the nPENIRQ and DAV signals */ QEMUTimer *timer; uint16_t model; @@ -63,7 +63,7 @@ typedef struct { } TSC2005State; enum { - TSC_MODE_XYZ_SCAN = 0x0, + TSC_MODE_XYZ_SCAN = 0x0, TSC_MODE_XY_SCAN, TSC_MODE_X, TSC_MODE_Y, @@ -82,100 +82,100 @@ enum { }; static const uint16_t mode_regs[16] = { - 0xf000, /* X, Y, Z scan */ - 0xc000, /* X, Y scan */ - 0x8000, /* X */ - 0x4000, /* Y */ - 0x3000, /* Z */ - 0x0800, /* AUX */ - 0x0400, /* TEMP1 */ - 0x0200, /* TEMP2 */ - 0x0800, /* AUX scan */ - 0x0040, /* X test */ - 0x0020, /* Y test */ - 0x0080, /* Short-circuit test */ - 0x0000, /* Reserved */ - 0x0000, /* X+, X- drivers */ - 0x0000, /* Y+, Y- drivers */ - 0x0000, /* Y+, X- drivers */ + 0xf000, /* X, Y, Z scan */ + 0xc000, /* X, Y scan */ + 0x8000, /* X */ + 0x4000, /* Y */ + 0x3000, /* Z */ + 0x0800, /* AUX */ + 0x0400, /* TEMP1 */ + 0x0200, /* TEMP2 */ + 0x0800, /* AUX scan */ + 0x0040, /* X test */ + 0x0020, /* Y test */ + 0x0080, /* Short-circuit test */ + 0x0000, /* Reserved */ + 0x0000, /* X+, X- drivers */ + 0x0000, /* Y+, Y- drivers */ + 0x0000, /* Y+, X- drivers */ }; -#define X_TRANSFORM(s) \ +#define X_TRANSFORM(s) \ ((s->y * s->tr[0] - s->x * s->tr[1]) / s->tr[2] + s->tr[3]) -#define Y_TRANSFORM(s) \ +#define Y_TRANSFORM(s) \ ((s->y * s->tr[4] - s->x * s->tr[5]) / s->tr[6] + s->tr[7]) -#define Z1_TRANSFORM(s) \ +#define Z1_TRANSFORM(s) \ ((400 - ((s)->x >> 7) + ((s)->pressure << 10)) << 4) -#define Z2_TRANSFORM(s) \ +#define Z2_TRANSFORM(s) \ ((4000 + ((s)->y >> 7) - ((s)->pressure << 10)) << 4) -#define AUX_VAL (700 << 4) /* +/- 3 at 12-bit */ -#define TEMP1_VAL (1264 << 4) /* +/- 5 at 12-bit */ -#define TEMP2_VAL (1531 << 4) /* +/- 5 at 12-bit */ +#define AUX_VAL (700 << 4) /* +/- 3 at 12-bit */ +#define TEMP1_VAL (1264 << 4) /* +/- 5 at 12-bit */ +#define TEMP2_VAL (1531 << 4) /* +/- 5 at 12-bit */ static uint16_t tsc2005_read(TSC2005State *s, int reg) { uint16_t ret; switch (reg) { - case 0x0: /* X */ + case 0x0: /* X */ s->dav &= ~mode_regs[TSC_MODE_X]; return TSC_CUT_RESOLUTION(X_TRANSFORM(s), s->precision) + (s->noise & 3); - case 0x1: /* Y */ + case 0x1: /* Y */ s->dav &= ~mode_regs[TSC_MODE_Y]; - s->noise ++; + s->noise++; return TSC_CUT_RESOLUTION(Y_TRANSFORM(s), s->precision) ^ (s->noise & 3); - case 0x2: /* Z1 */ + case 0x2: /* Z1 */ s->dav &= 0xdfff; return TSC_CUT_RESOLUTION(Z1_TRANSFORM(s), s->precision) - (s->noise & 3); - case 0x3: /* Z2 */ + case 0x3: /* Z2 */ s->dav &= 0xefff; return TSC_CUT_RESOLUTION(Z2_TRANSFORM(s), s->precision) | (s->noise & 3); - case 0x4: /* AUX */ + case 0x4: /* AUX */ s->dav &= ~mode_regs[TSC_MODE_AUX]; return TSC_CUT_RESOLUTION(AUX_VAL, s->precision); - case 0x5: /* TEMP1 */ + case 0x5: /* TEMP1 */ s->dav &= ~mode_regs[TSC_MODE_TEMP1]; return TSC_CUT_RESOLUTION(TEMP1_VAL, s->precision) - (s->noise & 5); - case 0x6: /* TEMP2 */ + case 0x6: /* TEMP2 */ s->dav &= 0xdfff; s->dav &= ~mode_regs[TSC_MODE_TEMP2]; return TSC_CUT_RESOLUTION(TEMP2_VAL, s->precision) ^ (s->noise & 3); - case 0x7: /* Status */ + case 0x7: /* Status */ ret = s->dav | (s->reset << 7) | (s->pdst << 2) | 0x0; s->dav &= ~(mode_regs[TSC_MODE_X_TEST] | mode_regs[TSC_MODE_Y_TEST] | mode_regs[TSC_MODE_TS_TEST]); s->reset = true; return ret; - case 0x8: /* AUX high threshold */ + case 0x8: /* AUX high threshold */ return s->aux_thr[1]; - case 0x9: /* AUX low threshold */ + case 0x9: /* AUX low threshold */ return s->aux_thr[0]; - case 0xa: /* TEMP high threshold */ + case 0xa: /* TEMP high threshold */ return s->temp_thr[1]; - case 0xb: /* TEMP low threshold */ + case 0xb: /* TEMP low threshold */ return s->temp_thr[0]; - case 0xc: /* CFR0 */ + case 0xc: /* CFR0 */ return (s->pressure << 15) | ((!s->busy) << 14) | - (s->nextprecision << 13) | s->timing[0]; - case 0xd: /* CFR1 */ + (s->nextprecision << 13) | s->timing[0]; + case 0xd: /* CFR1 */ return s->timing[1]; - case 0xe: /* CFR2 */ + case 0xe: /* CFR2 */ return (s->pin_func << 14) | s->filter; - case 0xf: /* Function select status */ + case 0xf: /* Function select status */ return s->function >= 0 ? 1 << s->function : 0; } @@ -200,13 +200,14 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data) s->temp_thr[0] = data; break; - case 0xc: /* CFR0 */ + case 0xc: /* CFR0 */ s->host_mode = (data >> 15) != 0; if (s->enabled != !(data & 0x4000)) { s->enabled = !(data & 0x4000); trace_tsc2005_sense(s->enabled ? "enabled" : "disabled"); - if (s->busy && !s->enabled) + if (s->busy && !s->enabled) { timer_del(s->timer); + } s->busy = s->busy && s->enabled; } s->nextprecision = (data >> 13) & 1; @@ -216,10 +217,10 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data) "tsc2005_write: illegal conversion clock setting\n"); } break; - case 0xd: /* CFR1 */ + case 0xd: /* CFR1 */ s->timing[1] = data & 0xf07; break; - case 0xe: /* CFR2 */ + case 0xe: /* CFR2 */ s->pin_func = (data >> 14) & 3; s->filter = data & 0x3fff; break; @@ -258,10 +259,12 @@ static void tsc2005_pin_update(TSC2005State *s) switch (s->nextfunction) { case TSC_MODE_XYZ_SCAN: case TSC_MODE_XY_SCAN: - if (!s->host_mode && s->dav) + if (!s->host_mode && s->dav) { s->enabled = false; - if (!s->pressure) + } + if (!s->pressure) { return; + } /* Fall through */ case TSC_MODE_AUX_SCAN: break; @@ -269,8 +272,9 @@ static void tsc2005_pin_update(TSC2005State *s) case TSC_MODE_X: case TSC_MODE_Y: case TSC_MODE_Z: - if (!s->pressure) + if (!s->pressure) { return; + } /* Fall through */ case TSC_MODE_AUX: case TSC_MODE_TEMP1: @@ -278,8 +282,9 @@ static void tsc2005_pin_update(TSC2005State *s) case TSC_MODE_X_TEST: case TSC_MODE_Y_TEST: case TSC_MODE_TS_TEST: - if (s->dav) + if (s->dav) { s->enabled = false; + } break; case TSC_MODE_RESERVED: @@ -290,13 +295,14 @@ static void tsc2005_pin_update(TSC2005State *s) return; } - if (!s->enabled || s->busy) + if (!s->enabled || s->busy) { return; + } s->busy = true; s->precision = s->nextprecision; s->function = s->nextfunction; - s->pdst = !s->pnd0; /* Synchronised on internal clock */ + s->pdst = !s->pnd0; /* Synchronised on internal clock */ expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (NANOSECONDS_PER_SECOND >> 7); timer_mod(s->timer, expires); @@ -331,7 +337,7 @@ static uint8_t tsc2005_txrx_word(void *opaque, uint8_t value) TSC2005State *s = opaque; uint32_t ret = 0; - switch (s->state ++) { + switch (s->state++) { case 0: if (value & 0x80) { /* Command */ @@ -343,8 +349,9 @@ static uint8_t tsc2005_txrx_word(void *opaque, uint8_t value) if (s->enabled != !(value & 1)) { s->enabled = !(value & 1); trace_tsc2005_sense(s->enabled ? "enabled" : "disabled"); - if (s->busy && !s->enabled) + if (s->busy && !s->enabled) { timer_del(s->timer); + } s->busy = s->busy && s->enabled; } tsc2005_pin_update(s); @@ -368,10 +375,11 @@ static uint8_t tsc2005_txrx_word(void *opaque, uint8_t value) break; case 1: - if (s->command) + if (s->command) { ret = (s->data >> 8) & 0xff; - else + } else { s->data |= value << 8; + } break; case 2: @@ -409,8 +417,9 @@ static void tsc2005_timer_tick(void *opaque) /* Timer ticked -- a set of conversions has been finished. */ - if (!s->busy) + if (!s->busy) { return; + } s->busy = false; s->dav |= mode_regs[s->function]; @@ -435,8 +444,9 @@ static void tsc2005_touchscreen_event(void *opaque, * signaling TS events immediately, but for now we simulate * the first conversion delay for sake of correctness. */ - if (p != s->pressure) + if (p != s->pressure) { tsc2005_pin_update(s); + } } static int tsc2005_post_load(void *opaque, int version_id) diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c index c4e32c7a42..b94e346af1 100644 --- a/hw/input/tsc210x.c +++ b/hw/input/tsc210x.c @@ -33,13 +33,13 @@ #include "migration/vmstate.h" #include "qapi/error.h" -#define TSC_DATA_REGISTERS_PAGE 0x0 -#define TSC_CONTROL_REGISTERS_PAGE 0x1 -#define TSC_AUDIO_REGISTERS_PAGE 0x2 +#define TSC_DATA_REGISTERS_PAGE 0x0 +#define TSC_CONTROL_REGISTERS_PAGE 0x1 +#define TSC_AUDIO_REGISTERS_PAGE 0x2 #define TSC_VERBOSE -#define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - resolution[p])) +#define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - resolution[p])) typedef struct { qemu_irq pint; @@ -105,60 +105,60 @@ typedef struct { static const int resolution[4] = { 12, 8, 10, 12 }; -#define TSC_MODE_NO_SCAN 0x0 -#define TSC_MODE_XY_SCAN 0x1 -#define TSC_MODE_XYZ_SCAN 0x2 -#define TSC_MODE_X 0x3 -#define TSC_MODE_Y 0x4 -#define TSC_MODE_Z 0x5 -#define TSC_MODE_BAT1 0x6 -#define TSC_MODE_BAT2 0x7 -#define TSC_MODE_AUX 0x8 -#define TSC_MODE_AUX_SCAN 0x9 -#define TSC_MODE_TEMP1 0xa -#define TSC_MODE_PORT_SCAN 0xb -#define TSC_MODE_TEMP2 0xc -#define TSC_MODE_XX_DRV 0xd -#define TSC_MODE_YY_DRV 0xe -#define TSC_MODE_YX_DRV 0xf +#define TSC_MODE_NO_SCAN 0x0 +#define TSC_MODE_XY_SCAN 0x1 +#define TSC_MODE_XYZ_SCAN 0x2 +#define TSC_MODE_X 0x3 +#define TSC_MODE_Y 0x4 +#define TSC_MODE_Z 0x5 +#define TSC_MODE_BAT1 0x6 +#define TSC_MODE_BAT2 0x7 +#define TSC_MODE_AUX 0x8 +#define TSC_MODE_AUX_SCAN 0x9 +#define TSC_MODE_TEMP1 0xa +#define TSC_MODE_PORT_SCAN 0xb +#define TSC_MODE_TEMP2 0xc +#define TSC_MODE_XX_DRV 0xd +#define TSC_MODE_YY_DRV 0xe +#define TSC_MODE_YX_DRV 0xf static const uint16_t mode_regs[16] = { - 0x0000, /* No scan */ - 0x0600, /* X, Y scan */ - 0x0780, /* X, Y, Z scan */ - 0x0400, /* X */ - 0x0200, /* Y */ - 0x0180, /* Z */ - 0x0040, /* BAT1 */ - 0x0030, /* BAT2 */ - 0x0010, /* AUX */ - 0x0010, /* AUX scan */ - 0x0004, /* TEMP1 */ - 0x0070, /* Port scan */ - 0x0002, /* TEMP2 */ - 0x0000, /* X+, X- drivers */ - 0x0000, /* Y+, Y- drivers */ - 0x0000, /* Y+, X- drivers */ + 0x0000, /* No scan */ + 0x0600, /* X, Y scan */ + 0x0780, /* X, Y, Z scan */ + 0x0400, /* X */ + 0x0200, /* Y */ + 0x0180, /* Z */ + 0x0040, /* BAT1 */ + 0x0030, /* BAT2 */ + 0x0010, /* AUX */ + 0x0010, /* AUX scan */ + 0x0004, /* TEMP1 */ + 0x0070, /* Port scan */ + 0x0002, /* TEMP2 */ + 0x0000, /* X+, X- drivers */ + 0x0000, /* Y+, Y- drivers */ + 0x0000, /* Y+, X- drivers */ }; -#define X_TRANSFORM(s) \ +#define X_TRANSFORM(s) \ ((s->y * s->tr[0] - s->x * s->tr[1]) / s->tr[2] + s->tr[3]) -#define Y_TRANSFORM(s) \ +#define Y_TRANSFORM(s) \ ((s->y * s->tr[4] - s->x * s->tr[5]) / s->tr[6] + s->tr[7]) -#define Z1_TRANSFORM(s) \ +#define Z1_TRANSFORM(s) \ ((400 - ((s)->x >> 7) + ((s)->pressure << 10)) << 4) -#define Z2_TRANSFORM(s) \ +#define Z2_TRANSFORM(s) \ ((4000 + ((s)->y >> 7) - ((s)->pressure << 10)) << 4) -#define BAT1_VAL 0x8660 -#define BAT2_VAL 0x0000 -#define AUX1_VAL 0x35c0 -#define AUX2_VAL 0xffff -#define TEMP1_VAL 0x8c70 -#define TEMP2_VAL 0xa5b0 +#define BAT1_VAL 0x8660 +#define BAT2_VAL 0x0000 +#define AUX1_VAL 0x35c0 +#define AUX2_VAL 0xffff +#define TEMP1_VAL 0x8c70 +#define TEMP2_VAL 0xa5b0 -#define TSC_POWEROFF_DELAY 50 -#define TSC_SOFTSTEP_DELAY 50 +#define TSC_POWEROFF_DELAY 50 +#define TSC_SOFTSTEP_DELAY 50 static void tsc210x_reset(TSC210xState *s) { @@ -224,34 +224,34 @@ typedef struct { int fsref; } TSC210xRateInfo; -/* { rate, dsor, fsref } */ +/* { rate, dsor, fsref } */ static const TSC210xRateInfo tsc2102_rates[] = { /* Fsref / 6.0 */ - { 7350, 63, 1 }, - { 8000, 63, 0 }, + { 7350, 63, 1 }, + { 8000, 63, 0 }, /* Fsref / 6.0 */ - { 7350, 54, 1 }, - { 8000, 54, 0 }, + { 7350, 54, 1 }, + { 8000, 54, 0 }, /* Fsref / 5.0 */ - { 8820, 45, 1 }, - { 9600, 45, 0 }, + { 8820, 45, 1 }, + { 9600, 45, 0 }, /* Fsref / 4.0 */ - { 11025, 36, 1 }, - { 12000, 36, 0 }, + { 11025, 36, 1 }, + { 12000, 36, 0 }, /* Fsref / 3.0 */ - { 14700, 27, 1 }, - { 16000, 27, 0 }, + { 14700, 27, 1 }, + { 16000, 27, 0 }, /* Fsref / 2.0 */ - { 22050, 18, 1 }, - { 24000, 18, 0 }, + { 22050, 18, 1 }, + { 24000, 18, 0 }, /* Fsref / 1.5 */ - { 29400, 9, 1 }, - { 32000, 9, 0 }, + { 29400, 9, 1 }, + { 32000, 9, 0 }, /* Fsref */ - { 44100, 0, 1 }, - { 48000, 0, 0 }, + { 44100, 0, 1 }, + { 48000, 0, 0 }, - { 0, 0, 0 }, + { 0, 0, 0 }, }; static inline void tsc210x_out_flush(TSC210xState *s, int len) @@ -259,12 +259,14 @@ static inline void tsc210x_out_flush(TSC210xState *s, int len) uint8_t *data = s->codec.out.fifo + s->codec.out.start; uint8_t *end = data + len; - while (data < end) + while (data < end) { data += AUD_write(s->dac_voice[0], data, end - data) ?: (end - data); + } s->codec.out.len -= len; - if (s->codec.out.len) + if (s->codec.out.len) { memmove(s->codec.out.fifo, end, s->codec.out.len); + } s->codec.out.start = 0; } @@ -285,11 +287,12 @@ static void tsc2102_audio_rate_update(TSC210xState *s) s->codec.tx_rate = 0; s->codec.rx_rate = 0; - if (s->dac_power & (1 << 15)) /* PWDNC */ + if (s->dac_power & (1 << 15)) { /* PWDNC */ return; + } - for (rate = tsc2102_rates; rate->rate; rate ++) - if (rate->dsor == (s->audio_ctrl1 & 0x3f) && /* DACFS */ + for (rate = tsc2102_rates; rate->rate; rate++) + if (rate->dsor == (s->audio_ctrl1 & 0x3f) && /* DACFS */ rate->fsref == ((s->audio_ctrl3 >> 13) & 1))/* REFFS */ break; if (!rate->rate) { @@ -315,10 +318,11 @@ static void tsc2102_audio_output_update(TSC210xState *s) s->codec.cts = 0; enable = - (~s->dac_power & (1 << 15)) && /* PWDNC */ - (~s->dac_power & (1 << 10)); /* DAPWDN */ - if (!enable || !s->codec.tx_rate) + (~s->dac_power & (1 << 15)) && /* PWDNC */ + (~s->dac_power & (1 << 10)); /* DAPWDN */ + if (!enable || !s->codec.tx_rate) { return; + } /* Force our own sampling rate even in slave DAC mode */ fmt.endianness = 0; @@ -337,28 +341,28 @@ static void tsc2102_audio_output_update(TSC210xState *s) static uint16_t tsc2102_data_register_read(TSC210xState *s, int reg) { switch (reg) { - case 0x00: /* X */ + case 0x00: /* X */ s->dav &= 0xfbff; return TSC_CUT_RESOLUTION(X_TRANSFORM(s), s->precision) + (s->noise & 3); - case 0x01: /* Y */ - s->noise ++; + case 0x01: /* Y */ + s->noise++; s->dav &= 0xfdff; return TSC_CUT_RESOLUTION(Y_TRANSFORM(s), s->precision) ^ (s->noise & 3); - case 0x02: /* Z1 */ + case 0x02: /* Z1 */ s->dav &= 0xfeff; return TSC_CUT_RESOLUTION(Z1_TRANSFORM(s), s->precision) - (s->noise & 3); - case 0x03: /* Z2 */ + case 0x03: /* Z2 */ s->dav &= 0xff7f; return TSC_CUT_RESOLUTION(Z2_TRANSFORM(s), s->precision) | (s->noise & 3); - case 0x04: /* KPData */ + case 0x04: /* KPData */ if ((s->model & 0xff00) == 0x2300) { if (s->kb.intr && (s->kb.mode & 2)) { s->kb.intr = 0; @@ -369,34 +373,34 @@ static uint16_t tsc2102_data_register_read(TSC210xState *s, int reg) return 0xffff; - case 0x05: /* BAT1 */ + case 0x05: /* BAT1 */ s->dav &= 0xffbf; return TSC_CUT_RESOLUTION(BAT1_VAL, s->precision) + (s->noise & 6); - case 0x06: /* BAT2 */ + case 0x06: /* BAT2 */ s->dav &= 0xffdf; return TSC_CUT_RESOLUTION(BAT2_VAL, s->precision); - case 0x07: /* AUX1 */ + case 0x07: /* AUX1 */ s->dav &= 0xffef; return TSC_CUT_RESOLUTION(AUX1_VAL, s->precision); - case 0x08: /* AUX2 */ + case 0x08: /* AUX2 */ s->dav &= 0xfff7; return 0xffff; - case 0x09: /* TEMP1 */ + case 0x09: /* TEMP1 */ s->dav &= 0xfffb; return TSC_CUT_RESOLUTION(TEMP1_VAL, s->precision) - (s->noise & 5); - case 0x0a: /* TEMP2 */ + case 0x0a: /* TEMP2 */ s->dav &= 0xfffd; return TSC_CUT_RESOLUTION(TEMP2_VAL, s->precision) ^ (s->noise & 3); - case 0x0b: /* DAC */ + case 0x0b: /* DAC */ s->dav &= 0xfffe; return 0xffff; @@ -413,11 +417,11 @@ static uint16_t tsc2102_control_register_read( TSC210xState *s, int reg) { switch (reg) { - case 0x00: /* TSC ADC */ + case 0x00: /* TSC ADC */ return (s->pressure << 15) | ((!s->busy) << 14) | - (s->nextfunction << 10) | (s->nextprecision << 8) | s->filter; + (s->nextfunction << 10) | (s->nextprecision << 8) | s->filter; - case 0x01: /* Status / Keypad Control */ + case 0x01: /* Status / Keypad Control */ if ((s->model & 0xff00) == 0x2100) return (s->pin_func << 14) | ((!s->enabled) << 13) | (s->host_mode << 12) | ((!!s->dav) << 11) | s->dav; @@ -425,29 +429,32 @@ static uint16_t tsc2102_control_register_read( return (s->kb.intr << 15) | ((s->kb.scan || !s->kb.down) << 14) | (s->kb.debounce << 11); - case 0x02: /* DAC Control */ - if ((s->model & 0xff00) == 0x2300) + case 0x02: /* DAC Control */ + if ((s->model & 0xff00) == 0x2300) { return s->dac_power & 0x8000; - else + } else { goto bad_reg; + } - case 0x03: /* Reference */ + case 0x03: /* Reference */ return s->ref; - case 0x04: /* Reset */ + case 0x04: /* Reset */ return 0xffff; - case 0x05: /* Configuration */ + case 0x05: /* Configuration */ return s->timing; - case 0x06: /* Secondary configuration */ - if ((s->model & 0xff00) == 0x2100) + case 0x06: /* Secondary configuration */ + if ((s->model & 0xff00) == 0x2100) { goto bad_reg; + } return ((!s->dav) << 15) | ((s->kb.mode & 1) << 14) | s->pll[2]; - case 0x10: /* Keypad Mask */ - if ((s->model & 0xff00) == 0x2100) + case 0x10: /* Keypad Mask */ + if ((s->model & 0xff00) == 0x2100) { goto bad_reg; + } return s->kb.mask; default: @@ -466,19 +473,19 @@ static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg) uint16_t val; switch (reg) { - case 0x00: /* Audio Control 1 */ + case 0x00: /* Audio Control 1 */ return s->audio_ctrl1; case 0x01: return 0xff00; - case 0x02: /* DAC Volume Control */ + case 0x02: /* DAC Volume Control */ return s->volume; case 0x03: return 0x8b00; - case 0x04: /* Audio Control 2 */ + case 0x04: /* Audio Control 2 */ l_ch = 1; r_ch = 1; if (s->softstep && !(s->dac_power & (1 << 10))) { @@ -490,46 +497,46 @@ static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg) return s->audio_ctrl2 | (l_ch << 3) | (r_ch << 2); - case 0x05: /* Stereo DAC Power Control */ + case 0x05: /* Stereo DAC Power Control */ return 0x2aa0 | s->dac_power | (((s->dac_power & (1 << 10)) && (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) > s->powerdown + TSC_POWEROFF_DELAY)) << 6); - case 0x06: /* Audio Control 3 */ + case 0x06: /* Audio Control 3 */ val = s->audio_ctrl3 | 0x0001; s->audio_ctrl3 &= 0xff3f; return val; - case 0x07: /* LCH_BASS_BOOST_N0 */ - case 0x08: /* LCH_BASS_BOOST_N1 */ - case 0x09: /* LCH_BASS_BOOST_N2 */ - case 0x0a: /* LCH_BASS_BOOST_N3 */ - case 0x0b: /* LCH_BASS_BOOST_N4 */ - case 0x0c: /* LCH_BASS_BOOST_N5 */ - case 0x0d: /* LCH_BASS_BOOST_D1 */ - case 0x0e: /* LCH_BASS_BOOST_D2 */ - case 0x0f: /* LCH_BASS_BOOST_D4 */ - case 0x10: /* LCH_BASS_BOOST_D5 */ - case 0x11: /* RCH_BASS_BOOST_N0 */ - case 0x12: /* RCH_BASS_BOOST_N1 */ - case 0x13: /* RCH_BASS_BOOST_N2 */ - case 0x14: /* RCH_BASS_BOOST_N3 */ - case 0x15: /* RCH_BASS_BOOST_N4 */ - case 0x16: /* RCH_BASS_BOOST_N5 */ - case 0x17: /* RCH_BASS_BOOST_D1 */ - case 0x18: /* RCH_BASS_BOOST_D2 */ - case 0x19: /* RCH_BASS_BOOST_D4 */ - case 0x1a: /* RCH_BASS_BOOST_D5 */ + case 0x07: /* LCH_BASS_BOOST_N0 */ + case 0x08: /* LCH_BASS_BOOST_N1 */ + case 0x09: /* LCH_BASS_BOOST_N2 */ + case 0x0a: /* LCH_BASS_BOOST_N3 */ + case 0x0b: /* LCH_BASS_BOOST_N4 */ + case 0x0c: /* LCH_BASS_BOOST_N5 */ + case 0x0d: /* LCH_BASS_BOOST_D1 */ + case 0x0e: /* LCH_BASS_BOOST_D2 */ + case 0x0f: /* LCH_BASS_BOOST_D4 */ + case 0x10: /* LCH_BASS_BOOST_D5 */ + case 0x11: /* RCH_BASS_BOOST_N0 */ + case 0x12: /* RCH_BASS_BOOST_N1 */ + case 0x13: /* RCH_BASS_BOOST_N2 */ + case 0x14: /* RCH_BASS_BOOST_N3 */ + case 0x15: /* RCH_BASS_BOOST_N4 */ + case 0x16: /* RCH_BASS_BOOST_N5 */ + case 0x17: /* RCH_BASS_BOOST_D1 */ + case 0x18: /* RCH_BASS_BOOST_D2 */ + case 0x19: /* RCH_BASS_BOOST_D4 */ + case 0x1a: /* RCH_BASS_BOOST_D5 */ return s->filter_data[reg - 0x07]; - case 0x1b: /* PLL Programmability 1 */ + case 0x1b: /* PLL Programmability 1 */ return s->pll[0]; - case 0x1c: /* PLL Programmability 2 */ + case 0x1c: /* PLL Programmability 2 */ return s->pll[1]; - case 0x1d: /* Audio Control 4 */ + case 0x1d: /* Audio Control 4 */ return (!s->softstep) << 14; default: @@ -545,16 +552,16 @@ static void tsc2102_data_register_write( TSC210xState *s, int reg, uint16_t value) { switch (reg) { - case 0x00: /* X */ - case 0x01: /* Y */ - case 0x02: /* Z1 */ - case 0x03: /* Z2 */ - case 0x05: /* BAT1 */ - case 0x06: /* BAT2 */ - case 0x07: /* AUX1 */ - case 0x08: /* AUX2 */ - case 0x09: /* TEMP1 */ - case 0x0a: /* TEMP2 */ + case 0x00: /* X */ + case 0x01: /* Y */ + case 0x02: /* Z1 */ + case 0x03: /* Z2 */ + case 0x05: /* BAT1 */ + case 0x06: /* BAT2 */ + case 0x07: /* AUX1 */ + case 0x08: /* AUX2 */ + case 0x09: /* TEMP1 */ + case 0x0a: /* TEMP2 */ return; default: @@ -567,18 +574,19 @@ static void tsc2102_control_register_write( TSC210xState *s, int reg, uint16_t value) { switch (reg) { - case 0x00: /* TSC ADC */ + case 0x00: /* TSC ADC */ s->host_mode = value >> 15; s->enabled = !(value & 0x4000); - if (s->busy && !s->enabled) + if (s->busy && !s->enabled) { timer_del(s->timer); + } s->busy = s->busy && s->enabled; s->nextfunction = (value >> 10) & 0xf; s->nextprecision = (value >> 8) & 3; s->filter = value & 0xff; return; - case 0x01: /* Status / Keypad Control */ + case 0x01: /* Status / Keypad Control */ if ((s->model & 0xff00) == 0x2100) s->pin_func = value >> 14; else { @@ -591,7 +599,7 @@ static void tsc2102_control_register_write( } return; - case 0x02: /* DAC Control */ + case 0x02: /* DAC Control */ if ((s->model & 0xff00) == 0x2300) { s->dac_power &= 0x7fff; s->dac_power |= 0x8000 & value; @@ -599,14 +607,15 @@ static void tsc2102_control_register_write( goto bad_reg; break; - case 0x03: /* Reference */ + case 0x03: /* Reference */ s->ref = value & 0x1f; return; - case 0x04: /* Reset */ + case 0x04: /* Reset */ if (value == 0xbb00) { - if (s->busy) + if (s->busy) { timer_del(s->timer); + } tsc210x_reset(s); #ifdef TSC_VERBOSE } else { @@ -616,7 +625,7 @@ static void tsc2102_control_register_write( } return; - case 0x05: /* Configuration */ + case 0x05: /* Configuration */ s->timing = value & 0x3f; #ifdef TSC_VERBOSE if (value & ~0x3f) @@ -625,16 +634,18 @@ static void tsc2102_control_register_write( #endif return; - case 0x06: /* Secondary configuration */ - if ((s->model & 0xff00) == 0x2100) + case 0x06: /* Secondary configuration */ + if ((s->model & 0xff00) == 0x2100) { goto bad_reg; + } s->kb.mode = value >> 14; s->pll[2] = value & 0x3ffff; return; - case 0x10: /* Keypad Mask */ - if ((s->model & 0xff00) == 0x2100) + case 0x10: /* Keypad Mask */ + if ((s->model & 0xff00) == 0x2100) { goto bad_reg; + } s->kb.mask = value; return; @@ -649,7 +660,7 @@ static void tsc2102_audio_register_write( TSC210xState *s, int reg, uint16_t value) { switch (reg) { - case 0x00: /* Audio Control 1 */ + case 0x00: /* Audio Control 1 */ s->audio_ctrl1 = value & 0x0f3f; #ifdef TSC_VERBOSE if ((value & ~0x0f3f) || ((value & 7) != ((value >> 3) & 7))) @@ -668,7 +679,7 @@ static void tsc2102_audio_register_write( #endif return; - case 0x02: /* DAC Volume Control */ + case 0x02: /* DAC Volume Control */ s->volume = value; s->volume_change = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); return; @@ -681,7 +692,7 @@ static void tsc2102_audio_register_write( #endif return; - case 0x04: /* Audio Control 2 */ + case 0x04: /* Audio Control 2 */ s->audio_ctrl2 = value & 0xf7f2; #ifdef TSC_VERBOSE if (value & ~0xf7fd) @@ -690,9 +701,10 @@ static void tsc2102_audio_register_write( #endif return; - case 0x05: /* Stereo DAC Power Control */ - if ((value & ~s->dac_power) & (1 << 10)) + case 0x05: /* Stereo DAC Power Control */ + if ((value & ~s->dac_power) & (1 << 10)) { s->powerdown = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } s->dac_power = value & 0x9543; #ifdef TSC_VERBOSE @@ -704,7 +716,7 @@ static void tsc2102_audio_register_write( tsc2102_audio_output_update(s); return; - case 0x06: /* Audio Control 3 */ + case 0x06: /* Audio Control 3 */ s->audio_ctrl3 &= 0x00c0; s->audio_ctrl3 |= value & 0xf800; #ifdef TSC_VERBOSE @@ -715,30 +727,30 @@ static void tsc2102_audio_register_write( tsc2102_audio_output_update(s); return; - case 0x07: /* LCH_BASS_BOOST_N0 */ - case 0x08: /* LCH_BASS_BOOST_N1 */ - case 0x09: /* LCH_BASS_BOOST_N2 */ - case 0x0a: /* LCH_BASS_BOOST_N3 */ - case 0x0b: /* LCH_BASS_BOOST_N4 */ - case 0x0c: /* LCH_BASS_BOOST_N5 */ - case 0x0d: /* LCH_BASS_BOOST_D1 */ - case 0x0e: /* LCH_BASS_BOOST_D2 */ - case 0x0f: /* LCH_BASS_BOOST_D4 */ - case 0x10: /* LCH_BASS_BOOST_D5 */ - case 0x11: /* RCH_BASS_BOOST_N0 */ - case 0x12: /* RCH_BASS_BOOST_N1 */ - case 0x13: /* RCH_BASS_BOOST_N2 */ - case 0x14: /* RCH_BASS_BOOST_N3 */ - case 0x15: /* RCH_BASS_BOOST_N4 */ - case 0x16: /* RCH_BASS_BOOST_N5 */ - case 0x17: /* RCH_BASS_BOOST_D1 */ - case 0x18: /* RCH_BASS_BOOST_D2 */ - case 0x19: /* RCH_BASS_BOOST_D4 */ - case 0x1a: /* RCH_BASS_BOOST_D5 */ + case 0x07: /* LCH_BASS_BOOST_N0 */ + case 0x08: /* LCH_BASS_BOOST_N1 */ + case 0x09: /* LCH_BASS_BOOST_N2 */ + case 0x0a: /* LCH_BASS_BOOST_N3 */ + case 0x0b: /* LCH_BASS_BOOST_N4 */ + case 0x0c: /* LCH_BASS_BOOST_N5 */ + case 0x0d: /* LCH_BASS_BOOST_D1 */ + case 0x0e: /* LCH_BASS_BOOST_D2 */ + case 0x0f: /* LCH_BASS_BOOST_D4 */ + case 0x10: /* LCH_BASS_BOOST_D5 */ + case 0x11: /* RCH_BASS_BOOST_N0 */ + case 0x12: /* RCH_BASS_BOOST_N1 */ + case 0x13: /* RCH_BASS_BOOST_N2 */ + case 0x14: /* RCH_BASS_BOOST_N3 */ + case 0x15: /* RCH_BASS_BOOST_N4 */ + case 0x16: /* RCH_BASS_BOOST_N5 */ + case 0x17: /* RCH_BASS_BOOST_D1 */ + case 0x18: /* RCH_BASS_BOOST_D2 */ + case 0x19: /* RCH_BASS_BOOST_D4 */ + case 0x1a: /* RCH_BASS_BOOST_D5 */ s->filter_data[reg - 0x07] = value; return; - case 0x1b: /* PLL Programmability 1 */ + case 0x1b: /* PLL Programmability 1 */ s->pll[0] = value & 0xfffc; #ifdef TSC_VERBOSE if (value & ~0xfffc) @@ -747,7 +759,7 @@ static void tsc2102_audio_register_write( #endif return; - case 0x1c: /* PLL Programmability 2 */ + case 0x1c: /* PLL Programmability 2 */ s->pll[1] = value & 0xfffc; #ifdef TSC_VERBOSE if (value & ~0xfffc) @@ -756,7 +768,7 @@ static void tsc2102_audio_register_write( #endif return; - case 0x1d: /* Audio Control 4 */ + case 0x1d: /* Audio Control 4 */ s->softstep = !(value & 0x4000); #ifdef TSC_VERBOSE if (value & ~0x4000) @@ -789,8 +801,9 @@ static void tsc210x_pin_update(TSC210xState *s) pin_state = s->pressure && !s->dav; } - if (!s->enabled) + if (!s->enabled) { pin_state = false; + } if (pin_state != s->irq) { s->irq = pin_state; @@ -800,23 +813,26 @@ static void tsc210x_pin_update(TSC210xState *s) switch (s->nextfunction) { case TSC_MODE_XY_SCAN: case TSC_MODE_XYZ_SCAN: - if (!s->pressure) + if (!s->pressure) { return; + } break; case TSC_MODE_X: case TSC_MODE_Y: case TSC_MODE_Z: - if (!s->pressure) + if (!s->pressure) { return; + } /* Fall through */ case TSC_MODE_BAT1: case TSC_MODE_BAT2: case TSC_MODE_AUX: case TSC_MODE_TEMP1: case TSC_MODE_TEMP2: - if (s->dav) + if (s->dav) { s->enabled = false; + } break; case TSC_MODE_AUX_SCAN: @@ -831,8 +847,9 @@ static void tsc210x_pin_update(TSC210xState *s) return; } - if (!s->enabled || s->busy || s->dav) + if (!s->enabled || s->busy || s->dav) { return; + } s->busy = true; s->precision = s->nextprecision; @@ -846,14 +863,16 @@ static uint16_t tsc210x_read(TSC210xState *s) { uint16_t ret = 0x0000; - if (!s->command) + if (!s->command) { fprintf(stderr, "tsc210x_read: SPI underrun!\n"); + } switch (s->page) { case TSC_DATA_REGISTERS_PAGE: ret = tsc2102_data_register_read(s, s->offset); - if (!s->dav) + if (!s->dav) { qemu_irq_raise(s->davint); + } break; case TSC_CONTROL_REGISTERS_PAGE: ret = tsc2102_control_register_read(s, s->offset); @@ -868,7 +887,7 @@ static uint16_t tsc210x_read(TSC210xState *s) tsc210x_pin_update(s); /* Allow sequential reads. */ - s->offset ++; + s->offset++; s->state = false; return ret; } @@ -921,10 +940,12 @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len) /* TODO: sequential reads etc - how do we make sure the host doesn't * unintentionally read out a conversion result from a register while * transmitting the command word of the next command? */ - if (!value || (s->state && s->command)) + if (!value || (s->state && s->command)) { ret = tsc210x_read(s); - if (value || (s->state && !s->command)) + } + if (value || (s->state && !s->command)) { tsc210x_write(s, value); + } return ret; } @@ -935,8 +956,9 @@ static void tsc210x_timer_tick(void *opaque) /* Timer ticked -- a set of conversions has been finished. */ - if (!s->busy) + if (!s->busy) { return; + } s->busy = false; s->dav |= mode_regs[s->function]; @@ -961,16 +983,18 @@ static void tsc210x_touchscreen_event(void *opaque, * signaling TS events immediately, but for now we simulate * the first conversion delay for sake of correctness. */ - if (p != s->pressure) + if (p != s->pressure) { tsc210x_pin_update(s); + } } static void tsc210x_i2s_swallow(TSC210xState *s) { - if (s->dac_voice[0]) + if (s->dac_voice[0]) { tsc210x_out_flush(s, s->codec.out.len); - else + } else { s->codec.out.len = 0; + } } static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out) @@ -1163,32 +1187,6 @@ I2SCodec *tsc210x_codec(uWireSlave *chip) void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info) { TSC210xState *s = (TSC210xState *) chip->opaque; -#if 0 - int64_t ltr[8]; - - ltr[0] = (int64_t) info->a[1] * info->y; - ltr[1] = (int64_t) info->a[4] * info->x; - ltr[2] = (int64_t) info->a[1] * info->a[3] - - (int64_t) info->a[4] * info->a[0]; - ltr[3] = (int64_t) info->a[2] * info->a[4] - - (int64_t) info->a[5] * info->a[1]; - ltr[4] = (int64_t) info->a[0] * info->y; - ltr[5] = (int64_t) info->a[3] * info->x; - ltr[6] = (int64_t) info->a[4] * info->a[0] - - (int64_t) info->a[1] * info->a[3]; - ltr[7] = (int64_t) info->a[2] * info->a[3] - - (int64_t) info->a[5] * info->a[0]; - - /* Avoid integer overflow */ - s->tr[0] = ltr[0] >> 11; - s->tr[1] = ltr[1] >> 11; - s->tr[2] = muldiv64(ltr[2], 1, info->a[6]); - s->tr[3] = muldiv64(ltr[3], 1 << 4, ltr[2]); - s->tr[4] = ltr[4] >> 11; - s->tr[5] = ltr[5] >> 11; - s->tr[6] = muldiv64(ltr[6], 1, info->a[6]); - s->tr[7] = muldiv64(ltr[7], 1 << 4, ltr[6]); -#else /* This version assumes touchscreen X & Y axis are parallel or * perpendicular to LCD's X & Y axis in some way. */ @@ -1218,17 +1216,17 @@ void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info) s->tr[4] >>= 11; s->tr[5] >>= 11; s->tr[7] <<= 4; -#endif } void tsc210x_key_event(uWireSlave *chip, int key, int down) { TSC210xState *s = (TSC210xState *) chip->opaque; - if (down) + if (down) { s->kb.down |= 1 << key; - else + } else { s->kb.down &= ~(1 << key); + } if (down && (s->kb.down & ~s->kb.mask) && !s->kb.intr) { s->kb.intr = 1; diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 435c47600f..4a5b413d0a 100644 --- a/hw/intc/omap_intc.c +++ b/hw/intc/omap_intc.c @@ -104,8 +104,8 @@ static inline void omap_inth_update(OMAPIntcState *s, int is_fiq) } } -#define INT_FALLING_EDGE 0 -#define INT_LOW_LEVEL 1 +#define INT_FALLING_EDGE 0 +#define INT_LOW_LEVEL 1 static void omap_set_intr(void *opaque, int irq, int req) { @@ -117,9 +117,9 @@ static void omap_set_intr(void *opaque, int irq, int req) if (req) { rise = ~bank->irqs & (1 << n); - if (~bank->sens_edge & (1 << n)) + if (~bank->sens_edge & (1 << n)) { rise &= ~bank->inputs; - + } bank->inputs |= (1 << n); if (rise) { bank->irqs |= rise; @@ -164,66 +164,69 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr, offset &= 0xff; switch (offset) { - case 0x00: /* ITR */ + case 0x00: /* ITR */ return bank->irqs; - case 0x04: /* MIR */ + case 0x04: /* MIR */ return bank->mask; - case 0x10: /* SIR_IRQ_CODE */ + case 0x10: /* SIR_IRQ_CODE */ case 0x14: /* SIR_FIQ_CODE */ - if (bank_no != 0) + if (bank_no != 0) { break; + } line_no = s->sir_intr[(offset - 0x10) >> 2]; bank = &s->bank[line_no >> 5]; i = line_no & 31; - if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) + if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) { bank->irqs &= ~(1 << i); + } return line_no; - case 0x18: /* CONTROL_REG */ - if (bank_no != 0) + case 0x18: /* CONTROL_REG */ + if (bank_no != 0) { break; + } return 0; - case 0x1c: /* ILR0 */ - case 0x20: /* ILR1 */ - case 0x24: /* ILR2 */ - case 0x28: /* ILR3 */ - case 0x2c: /* ILR4 */ - case 0x30: /* ILR5 */ - case 0x34: /* ILR6 */ - case 0x38: /* ILR7 */ - case 0x3c: /* ILR8 */ - case 0x40: /* ILR9 */ - case 0x44: /* ILR10 */ - case 0x48: /* ILR11 */ - case 0x4c: /* ILR12 */ - case 0x50: /* ILR13 */ - case 0x54: /* ILR14 */ - case 0x58: /* ILR15 */ - case 0x5c: /* ILR16 */ - case 0x60: /* ILR17 */ - case 0x64: /* ILR18 */ - case 0x68: /* ILR19 */ - case 0x6c: /* ILR20 */ - case 0x70: /* ILR21 */ - case 0x74: /* ILR22 */ - case 0x78: /* ILR23 */ - case 0x7c: /* ILR24 */ - case 0x80: /* ILR25 */ - case 0x84: /* ILR26 */ - case 0x88: /* ILR27 */ - case 0x8c: /* ILR28 */ - case 0x90: /* ILR29 */ - case 0x94: /* ILR30 */ - case 0x98: /* ILR31 */ + case 0x1c: /* ILR0 */ + case 0x20: /* ILR1 */ + case 0x24: /* ILR2 */ + case 0x28: /* ILR3 */ + case 0x2c: /* ILR4 */ + case 0x30: /* ILR5 */ + case 0x34: /* ILR6 */ + case 0x38: /* ILR7 */ + case 0x3c: /* ILR8 */ + case 0x40: /* ILR9 */ + case 0x44: /* ILR10 */ + case 0x48: /* ILR11 */ + case 0x4c: /* ILR12 */ + case 0x50: /* ILR13 */ + case 0x54: /* ILR14 */ + case 0x58: /* ILR15 */ + case 0x5c: /* ILR16 */ + case 0x60: /* ILR17 */ + case 0x64: /* ILR18 */ + case 0x68: /* ILR19 */ + case 0x6c: /* ILR20 */ + case 0x70: /* ILR21 */ + case 0x74: /* ILR22 */ + case 0x78: /* ILR23 */ + case 0x7c: /* ILR24 */ + case 0x80: /* ILR25 */ + case 0x84: /* ILR26 */ + case 0x88: /* ILR27 */ + case 0x8c: /* ILR28 */ + case 0x90: /* ILR29 */ + case 0x94: /* ILR30 */ + case 0x98: /* ILR31 */ i = (offset - 0x1c) >> 2; return (bank->priority[i] << 2) | (((bank->sens_edge >> i) & 1) << 1) | ((bank->fiq >> i) & 1); - case 0x9c: /* ISR */ + case 0x9c: /* ISR */ return 0x00000000; } @@ -241,26 +244,27 @@ static void omap_inth_write(void *opaque, hwaddr addr, offset &= 0xff; switch (offset) { - case 0x00: /* ITR */ + case 0x00: /* ITR */ /* Important: ignore the clearing if the IRQ is level-triggered and the input bit is 1 */ bank->irqs &= value | (bank->inputs & bank->sens_edge); return; - case 0x04: /* MIR */ + case 0x04: /* MIR */ bank->mask = value; omap_inth_update(s, 0); omap_inth_update(s, 1); return; - case 0x10: /* SIR_IRQ_CODE */ - case 0x14: /* SIR_FIQ_CODE */ + case 0x10: /* SIR_IRQ_CODE */ + case 0x14: /* SIR_FIQ_CODE */ OMAP_RO_REG(addr); break; - case 0x18: /* CONTROL_REG */ - if (bank_no != 0) + case 0x18: /* CONTROL_REG */ + if (bank_no != 0) { break; + } if (value & 2) { qemu_set_irq(s->parent_intr[1], 0); s->new_agr[1] = ~0; @@ -273,38 +277,38 @@ static void omap_inth_write(void *opaque, hwaddr addr, } return; - case 0x1c: /* ILR0 */ - case 0x20: /* ILR1 */ - case 0x24: /* ILR2 */ - case 0x28: /* ILR3 */ - case 0x2c: /* ILR4 */ - case 0x30: /* ILR5 */ - case 0x34: /* ILR6 */ - case 0x38: /* ILR7 */ - case 0x3c: /* ILR8 */ - case 0x40: /* ILR9 */ - case 0x44: /* ILR10 */ - case 0x48: /* ILR11 */ - case 0x4c: /* ILR12 */ - case 0x50: /* ILR13 */ - case 0x54: /* ILR14 */ - case 0x58: /* ILR15 */ - case 0x5c: /* ILR16 */ - case 0x60: /* ILR17 */ - case 0x64: /* ILR18 */ - case 0x68: /* ILR19 */ - case 0x6c: /* ILR20 */ - case 0x70: /* ILR21 */ - case 0x74: /* ILR22 */ - case 0x78: /* ILR23 */ - case 0x7c: /* ILR24 */ - case 0x80: /* ILR25 */ - case 0x84: /* ILR26 */ - case 0x88: /* ILR27 */ - case 0x8c: /* ILR28 */ - case 0x90: /* ILR29 */ - case 0x94: /* ILR30 */ - case 0x98: /* ILR31 */ + case 0x1c: /* ILR0 */ + case 0x20: /* ILR1 */ + case 0x24: /* ILR2 */ + case 0x28: /* ILR3 */ + case 0x2c: /* ILR4 */ + case 0x30: /* ILR5 */ + case 0x34: /* ILR6 */ + case 0x38: /* ILR7 */ + case 0x3c: /* ILR8 */ + case 0x40: /* ILR9 */ + case 0x44: /* ILR10 */ + case 0x48: /* ILR11 */ + case 0x4c: /* ILR12 */ + case 0x50: /* ILR13 */ + case 0x54: /* ILR14 */ + case 0x58: /* ILR15 */ + case 0x5c: /* ILR16 */ + case 0x60: /* ILR17 */ + case 0x64: /* ILR18 */ + case 0x68: /* ILR19 */ + case 0x6c: /* ILR20 */ + case 0x70: /* ILR21 */ + case 0x74: /* ILR22 */ + case 0x78: /* ILR23 */ + case 0x7c: /* ILR24 */ + case 0x80: /* ILR25 */ + case 0x84: /* ILR26 */ + case 0x88: /* ILR27 */ + case 0x8c: /* ILR28 */ + case 0x90: /* ILR29 */ + case 0x94: /* ILR30 */ + case 0x98: /* ILR31 */ i = (offset - 0x1c) >> 2; bank->priority[i] = (value >> 2) & 0x1f; bank->sens_edge &= ~(1 << i); @@ -313,8 +317,8 @@ static void omap_inth_write(void *opaque, hwaddr addr, bank->fiq |= (value & 1) << i; return; - case 0x9c: /* ISR */ - for (i = 0; i < 32; i ++) + case 0x9c: /* ISR */ + for (i = 0; i < 32; i++) if (value & (1 << i)) { omap_set_intr(s, 32 * bank_no + i, 1); return; @@ -339,7 +343,7 @@ static void omap_inth_reset(DeviceState *dev) OMAPIntcState *s = OMAP_INTC(dev); int i; - for (i = 0; i < s->nbanks; ++i){ + for (i = 0; i < s->nbanks; ++i) { s->bank[i].irqs = 0x00000000; s->bank[i].mask = 0xffffffff; s->bank[i].sens_edge = 0x00000000; @@ -348,8 +352,9 @@ static void omap_inth_reset(DeviceState *dev) s->bank[i].swi = 0x00000000; memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); - if (s->level_only) + if (s->level_only) { s->bank[i].sens_edge = 0xffffffff; + } } s->new_agr[0] = ~0; @@ -440,58 +445,59 @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr, } switch (offset) { - case 0x00: /* INTC_REVISION */ + case 0x00: /* INTC_REVISION */ return s->revision; - case 0x10: /* INTC_SYSCONFIG */ + case 0x10: /* INTC_SYSCONFIG */ return (s->autoidle >> 2) & 1; - case 0x14: /* INTC_SYSSTATUS */ - return 1; /* RESETDONE */ + case 0x14: /* INTC_SYSSTATUS */ + return 1; /* RESETDONE */ - case 0x40: /* INTC_SIR_IRQ */ + case 0x40: /* INTC_SIR_IRQ */ return s->sir_intr[0]; - case 0x44: /* INTC_SIR_FIQ */ + case 0x44: /* INTC_SIR_FIQ */ return s->sir_intr[1]; - case 0x48: /* INTC_CONTROL */ - return (!s->mask) << 2; /* GLOBALMASK */ + case 0x48: /* INTC_CONTROL */ + return (!s->mask) << 2; /* GLOBALMASK */ - case 0x4c: /* INTC_PROTECTION */ + case 0x4c: /* INTC_PROTECTION */ return 0; - case 0x50: /* INTC_IDLE */ + case 0x50: /* INTC_IDLE */ return s->autoidle & 3; /* Per-bank registers */ - case 0x80: /* INTC_ITR */ + case 0x80: /* INTC_ITR */ return bank->inputs; - case 0x84: /* INTC_MIR */ + case 0x84: /* INTC_MIR */ return bank->mask; - case 0x88: /* INTC_MIR_CLEAR */ - case 0x8c: /* INTC_MIR_SET */ + case 0x88: /* INTC_MIR_CLEAR */ + case 0x8c: /* INTC_MIR_SET */ return 0; - case 0x90: /* INTC_ISR_SET */ + case 0x90: /* INTC_ISR_SET */ return bank->swi; - case 0x94: /* INTC_ISR_CLEAR */ + case 0x94: /* INTC_ISR_CLEAR */ return 0; - case 0x98: /* INTC_PENDING_IRQ */ + case 0x98: /* INTC_PENDING_IRQ */ return bank->irqs & ~bank->mask & ~bank->fiq; - case 0x9c: /* INTC_PENDING_FIQ */ + case 0x9c: /* INTC_PENDING_FIQ */ return bank->irqs & ~bank->mask & bank->fiq; /* Per-line registers */ - case 0x100 ... 0x300: /* INTC_ILR */ + case 0x100 ... 0x300: /* INTC_ILR */ bank_no = (offset - 0x100) >> 7; - if (bank_no > s->nbanks) + if (bank_no > s->nbanks) { break; + } bank = &s->bank[bank_no]; line_no = (offset & 0x7f) >> 2; return (bank->priority[line_no] << 2) | @@ -521,7 +527,7 @@ static void omap2_inth_write(void *opaque, hwaddr addr, } switch (offset) { - case 0x10: /* INTC_SYSCONFIG */ + case 0x10: /* INTC_SYSCONFIG */ s->autoidle &= 4; s->autoidle |= (value & 1) << 2; if (value & 2) { /* SOFTRESET */ @@ -529,21 +535,21 @@ static void omap2_inth_write(void *opaque, hwaddr addr, } return; - case 0x48: /* INTC_CONTROL */ - s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ - if (value & 2) { /* NEWFIQAGR */ + case 0x48: /* INTC_CONTROL */ + s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ + if (value & 2) { /* NEWFIQAGR */ qemu_set_irq(s->parent_intr[1], 0); s->new_agr[1] = ~0; omap_inth_update(s, 1); } - if (value & 1) { /* NEWIRQAGR */ + if (value & 1) { /* NEWIRQAGR */ qemu_set_irq(s->parent_intr[0], 0); s->new_agr[0] = ~0; omap_inth_update(s, 0); } return; - case 0x4c: /* INTC_PROTECTION */ + case 0x4c: /* INTC_PROTECTION */ /* TODO: Make a bitmap (or sizeof(char)map) of access privileges * for every register, see Chapter 3 and 4 for privileged mode. */ if (value & 1) @@ -551,44 +557,45 @@ static void omap2_inth_write(void *opaque, hwaddr addr, __func__); return; - case 0x50: /* INTC_IDLE */ + case 0x50: /* INTC_IDLE */ s->autoidle &= ~3; s->autoidle |= value & 3; return; /* Per-bank registers */ - case 0x84: /* INTC_MIR */ + case 0x84: /* INTC_MIR */ bank->mask = value; omap_inth_update(s, 0); omap_inth_update(s, 1); return; - case 0x88: /* INTC_MIR_CLEAR */ + case 0x88: /* INTC_MIR_CLEAR */ bank->mask &= ~value; omap_inth_update(s, 0); omap_inth_update(s, 1); return; - case 0x8c: /* INTC_MIR_SET */ + case 0x8c: /* INTC_MIR_SET */ bank->mask |= value; return; - case 0x90: /* INTC_ISR_SET */ + case 0x90: /* INTC_ISR_SET */ bank->irqs |= bank->swi |= value; omap_inth_update(s, 0); omap_inth_update(s, 1); return; - case 0x94: /* INTC_ISR_CLEAR */ + case 0x94: /* INTC_ISR_CLEAR */ bank->swi &= ~value; bank->irqs = bank->swi & bank->inputs; return; /* Per-line registers */ - case 0x100 ... 0x300: /* INTC_ILR */ + case 0x100 ... 0x300: /* INTC_ILR */ bank_no = (offset - 0x100) >> 7; - if (bank_no > s->nbanks) + if (bank_no > s->nbanks) { break; + } bank = &s->bank[bank_no]; line_no = (offset & 0x7f) >> 2; bank->priority[line_no] = (value >> 2) & 0x3f; @@ -596,13 +603,13 @@ static void omap2_inth_write(void *opaque, hwaddr addr, bank->fiq |= (value & 1) << line_no; return; - case 0x00: /* INTC_REVISION */ - case 0x14: /* INTC_SYSSTATUS */ - case 0x40: /* INTC_SIR_IRQ */ - case 0x44: /* INTC_SIR_FIQ */ - case 0x80: /* INTC_ITR */ - case 0x98: /* INTC_PENDING_IRQ */ - case 0x9c: /* INTC_PENDING_FIQ */ + case 0x00: /* INTC_REVISION */ + case 0x14: /* INTC_SYSSTATUS */ + case 0x40: /* INTC_SIR_IRQ */ + case 0x44: /* INTC_SIR_FIQ */ + case 0x80: /* INTC_ITR */ + case 0x98: /* INTC_PENDING_IRQ */ + case 0x9c: /* INTC_PENDING_FIQ */ OMAP_RO_REG(addr); return; } diff --git a/hw/misc/cbus.c b/hw/misc/cbus.c index 653e8ddcd5..a09232e755 100644 --- a/hw/misc/cbus.c +++ b/hw/misc/cbus.c @@ -26,7 +26,7 @@ #include "hw/misc/cbus.h" #include "sysemu/runstate.h" -//#define DEBUG +/*#define DEBUG*/ typedef struct { void *opaque; @@ -78,13 +78,15 @@ static void cbus_cycle(CBusPriv *s) s->dir = !s->rw; s->val = 0; - if (s->rw) + if (s->rw) { cbus_io(s); + } break; case cbus_value: - if (!s->rw) + if (!s->rw) { cbus_io(s); + } s->cycle = cbus_address; s->bit = 8; @@ -99,13 +101,15 @@ static void cbus_clk(void *opaque, int line, int level) CBusPriv *s = (CBusPriv *) opaque; if (!s->sel && level && !s->clk) { - if (s->dir) - s->val |= s->dat << (s->bit --); - else - qemu_set_irq(s->dat_out, (s->val >> (s->bit --)) & 1); + if (s->dir) { + s->val |= s->dat << (s->bit--); + } else { + qemu_set_irq(s->dat_out, (s->val >> (s->bit--)) & 1); + } - if (s->bit < 0) + if (s->bit < 0) { cbus_cycle(s); + } } s->clk = level; @@ -179,61 +183,61 @@ static void retu_interrupt_update(CBusRetu *s) qemu_set_irq(s->irq, s->irqst & ~s->irqen); } -#define RETU_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ -#define RETU_REG_IDR 0x01 /* (T) Interrupt ID */ -#define RETU_REG_IMR 0x02 /* (RW) Interrupt mask */ -#define RETU_REG_RTCDSR 0x03 /* (RW) RTC seconds register */ -#define RETU_REG_RTCHMR 0x04 /* (RO) RTC hours and minutes reg */ -#define RETU_REG_RTCHMAR 0x05 /* (RW) RTC hours and minutes set reg */ -#define RETU_REG_RTCCALR 0x06 /* (RW) RTC calibration register */ -#define RETU_REG_ADCR 0x08 /* (RW) ADC result register */ -#define RETU_REG_ADCSCR 0x09 /* (RW) ADC sample control register */ -#define RETU_REG_AFCR 0x0a /* (RW) AFC register */ -#define RETU_REG_ANTIFR 0x0b /* (RW) AntiF register */ -#define RETU_REG_CALIBR 0x0c /* (RW) CalibR register*/ -#define RETU_REG_CCR1 0x0d /* (RW) Common control register 1 */ -#define RETU_REG_CCR2 0x0e /* (RW) Common control register 2 */ -#define RETU_REG_RCTRL_CLR 0x0f /* (T) Regulator clear register */ -#define RETU_REG_RCTRL_SET 0x10 /* (T) Regulator set register */ -#define RETU_REG_TXCR 0x11 /* (RW) TxC register */ -#define RETU_REG_STATUS 0x16 /* (RO) Status register */ -#define RETU_REG_WATCHDOG 0x17 /* (RW) Watchdog register */ -#define RETU_REG_AUDTXR 0x18 /* (RW) Audio Codec Tx register */ -#define RETU_REG_AUDPAR 0x19 /* (RW) AudioPA register */ -#define RETU_REG_AUDRXR1 0x1a /* (RW) Audio receive register 1 */ -#define RETU_REG_AUDRXR2 0x1b /* (RW) Audio receive register 2 */ -#define RETU_REG_SGR1 0x1c /* (RW) */ -#define RETU_REG_SCR1 0x1d /* (RW) */ -#define RETU_REG_SGR2 0x1e /* (RW) */ -#define RETU_REG_SCR2 0x1f /* (RW) */ +#define RETU_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ +#define RETU_REG_IDR 0x01 /* (T) Interrupt ID */ +#define RETU_REG_IMR 0x02 /* (RW) Interrupt mask */ +#define RETU_REG_RTCDSR 0x03 /* (RW) RTC seconds register */ +#define RETU_REG_RTCHMR 0x04 /* (RO) RTC hours and minutes reg */ +#define RETU_REG_RTCHMAR 0x05 /* (RW) RTC hours and minutes set reg */ +#define RETU_REG_RTCCALR 0x06 /* (RW) RTC calibration register */ +#define RETU_REG_ADCR 0x08 /* (RW) ADC result register */ +#define RETU_REG_ADCSCR 0x09 /* (RW) ADC sample control register */ +#define RETU_REG_AFCR 0x0a /* (RW) AFC register */ +#define RETU_REG_ANTIFR 0x0b /* (RW) AntiF register */ +#define RETU_REG_CALIBR 0x0c /* (RW) CalibR register*/ +#define RETU_REG_CCR1 0x0d /* (RW) Common control register 1 */ +#define RETU_REG_CCR2 0x0e /* (RW) Common control register 2 */ +#define RETU_REG_RCTRL_CLR 0x0f /* (T) Regulator clear register */ +#define RETU_REG_RCTRL_SET 0x10 /* (T) Regulator set register */ +#define RETU_REG_TXCR 0x11 /* (RW) TxC register */ +#define RETU_REG_STATUS 0x16 /* (RO) Status register */ +#define RETU_REG_WATCHDOG 0x17 /* (RW) Watchdog register */ +#define RETU_REG_AUDTXR 0x18 /* (RW) Audio Codec Tx register */ +#define RETU_REG_AUDPAR 0x19 /* (RW) AudioPA register */ +#define RETU_REG_AUDRXR1 0x1a /* (RW) Audio receive register 1 */ +#define RETU_REG_AUDRXR2 0x1b /* (RW) Audio receive register 2 */ +#define RETU_REG_SGR1 0x1c /* (RW) */ +#define RETU_REG_SCR1 0x1d /* (RW) */ +#define RETU_REG_SGR2 0x1e /* (RW) */ +#define RETU_REG_SCR2 0x1f /* (RW) */ /* Retu Interrupt sources */ enum { - retu_int_pwr = 0, /* Power button */ - retu_int_char = 1, /* Charger */ - retu_int_rtcs = 2, /* Seconds */ - retu_int_rtcm = 3, /* Minutes */ - retu_int_rtcd = 4, /* Days */ - retu_int_rtca = 5, /* Alarm */ - retu_int_hook = 6, /* Hook */ - retu_int_head = 7, /* Headset */ - retu_int_adcs = 8, /* ADC sample */ + retu_int_pwr = 0, /* Power button */ + retu_int_char = 1, /* Charger */ + retu_int_rtcs = 2, /* Seconds */ + retu_int_rtcm = 3, /* Minutes */ + retu_int_rtcd = 4, /* Days */ + retu_int_rtca = 5, /* Alarm */ + retu_int_hook = 6, /* Hook */ + retu_int_head = 7, /* Headset */ + retu_int_adcs = 8, /* ADC sample */ }; /* Retu ADC channel wiring */ enum { - retu_adc_bsi = 1, /* BSI */ - retu_adc_batt_temp = 2, /* Battery temperature */ - retu_adc_chg_volt = 3, /* Charger voltage */ - retu_adc_head_det = 4, /* Headset detection */ - retu_adc_hook_det = 5, /* Hook detection */ - retu_adc_rf_gp = 6, /* RF GP */ - retu_adc_tx_det = 7, /* Wideband Tx detection */ - retu_adc_batt_volt = 8, /* Battery voltage */ - retu_adc_sens = 10, /* Light sensor */ - retu_adc_sens_temp = 11, /* Light sensor temperature */ - retu_adc_bbatt_volt = 12, /* Backup battery voltage */ - retu_adc_self_temp = 13, /* RETU temperature */ + retu_adc_bsi = 1, /* BSI */ + retu_adc_batt_temp = 2, /* Battery temperature */ + retu_adc_chg_volt = 3, /* Charger voltage */ + retu_adc_head_det = 4, /* Headset detection */ + retu_adc_hook_det = 5, /* Hook detection */ + retu_adc_rf_gp = 6, /* RF GP */ + retu_adc_tx_det = 7, /* Wideband Tx detection */ + retu_adc_batt_volt = 8, /* Battery voltage */ + retu_adc_sens = 10, /* Light sensor */ + retu_adc_sens_temp = 11, /* Light sensor temperature */ + retu_adc_bbatt_volt = 12, /* Backup battery voltage */ + retu_adc_self_temp = 13, /* RETU temperature */ }; static inline uint16_t retu_read(CBusRetu *s, int reg) @@ -246,7 +250,7 @@ static inline uint16_t retu_read(CBusRetu *s, int reg) case RETU_REG_ASICR: return 0x0215 | (s->is_vilma << 7); - case RETU_REG_IDR: /* TODO: Or is this ffs(s->irqst)? */ + case RETU_REG_IDR: /* TODO: Or is this ffs(s->irqst)? */ return s->irqst; case RETU_REG_IMR: @@ -355,8 +359,9 @@ static inline void retu_write(CBusRetu *s, int reg, uint16_t val) break; case RETU_REG_WATCHDOG: - if (val == 0 && (s->cc[0] & 2)) + if (val == 0 && (s->cc[0] & 2)) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } break; case RETU_REG_TXCR: @@ -380,10 +385,11 @@ static void retu_io(void *opaque, int rw, int reg, uint16_t *val) { CBusRetu *s = (CBusRetu *) opaque; - if (rw) + if (rw) { *val = retu_read(s, reg); - else + } else { retu_write(s, reg, *val); + } } void *retu_init(qemu_irq irq, int vilma) @@ -424,47 +430,12 @@ void retu_key_event(void *retu, int state) s->irqst |= 1 << retu_int_pwr; retu_interrupt_update(s); - if (state) + if (state) { s->status &= ~(1 << 5); - else + } else { s->status |= 1 << 5; -} - -#if 0 -static void retu_head_event(void *retu, int state) -{ - CBusSlave *slave = (CBusSlave *) retu; - CBusRetu *s = (CBusRetu *) slave->opaque; - - if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */ - /* TODO: reissue the interrupt every 100ms or so. */ - s->irqst |= 1 << retu_int_head; - retu_interrupt_update(s); } - - if (state) - s->result[retu_adc_head_det] = 50; - else - s->result[retu_adc_head_det] = 123; -} - -static void retu_hook_event(void *retu, int state) -{ - CBusSlave *slave = (CBusSlave *) retu; - CBusRetu *s = (CBusRetu *) slave->opaque; - - if ((s->cc[0] & 0x500) == 0x500) { - /* TODO: reissue the interrupt every 100ms or so. */ - s->irqst |= 1 << retu_int_hook; - retu_interrupt_update(s); - } - - if (state) - s->result[retu_adc_hook_det] = 50; - else - s->result[retu_adc_hook_det] = 123; } -#endif /* Tahvo/Betty */ typedef struct { @@ -485,20 +456,20 @@ static void tahvo_interrupt_update(CBusTahvo *s) qemu_set_irq(s->irq, s->irqst & ~s->irqen); } -#define TAHVO_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ -#define TAHVO_REG_IDR 0x01 /* (T) Interrupt ID */ -#define TAHVO_REG_IDSR 0x02 /* (RO) Interrupt status */ -#define TAHVO_REG_IMR 0x03 /* (RW) Interrupt mask */ -#define TAHVO_REG_CHAPWMR 0x04 /* (RW) Charger PWM */ -#define TAHVO_REG_LEDPWMR 0x05 /* (RW) LED PWM */ -#define TAHVO_REG_USBR 0x06 /* (RW) USB control */ -#define TAHVO_REG_RCR 0x07 /* (RW) Some kind of power management */ -#define TAHVO_REG_CCR1 0x08 /* (RW) Common control register 1 */ -#define TAHVO_REG_CCR2 0x09 /* (RW) Common control register 2 */ -#define TAHVO_REG_TESTR1 0x0a /* (RW) Test register 1 */ -#define TAHVO_REG_TESTR2 0x0b /* (RW) Test register 2 */ -#define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */ -#define TAHVO_REG_FRR 0x0d /* (RO) FR */ +#define TAHVO_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ +#define TAHVO_REG_IDR 0x01 /* (T) Interrupt ID */ +#define TAHVO_REG_IDSR 0x02 /* (RO) Interrupt status */ +#define TAHVO_REG_IMR 0x03 /* (RW) Interrupt mask */ +#define TAHVO_REG_CHAPWMR 0x04 /* (RW) Charger PWM */ +#define TAHVO_REG_LEDPWMR 0x05 /* (RW) LED PWM */ +#define TAHVO_REG_USBR 0x06 /* (RW) USB control */ +#define TAHVO_REG_RCR 0x07 /* (RW) Some kind of power management */ +#define TAHVO_REG_CCR1 0x08 /* (RW) Common control register 1 */ +#define TAHVO_REG_CCR2 0x09 /* (RW) Common control register 2 */ +#define TAHVO_REG_TESTR1 0x0a /* (RW) Test register 1 */ +#define TAHVO_REG_TESTR2 0x0b /* (RW) Test register 2 */ +#define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */ +#define TAHVO_REG_FRR 0x0d /* (RO) FR */ static inline uint16_t tahvo_read(CBusTahvo *s, int reg) { @@ -508,10 +479,10 @@ static inline uint16_t tahvo_read(CBusTahvo *s, int reg) switch (reg) { case TAHVO_REG_ASICR: - return 0x0021 | (s->is_betty ? 0x0b00 : 0x0300); /* 22 in N810 */ + return 0x0021 | (s->is_betty ? 0x0b00 : 0x0300); /* 22 in N810 */ case TAHVO_REG_IDR: - case TAHVO_REG_IDSR: /* XXX: what does this do? */ + case TAHVO_REG_IDSR: /* XXX: what does this do? */ return s->irqst; case TAHVO_REG_IMR: @@ -596,10 +567,11 @@ static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val) { CBusTahvo *s = (CBusTahvo *) opaque; - if (rw) + if (rw) { *val = tahvo_read(s, reg); - else + } else { tahvo_write(s, reg, *val); + } } void *tahvo_init(qemu_irq irq, int betty) diff --git a/hw/misc/omap_clk.c b/hw/misc/omap_clk.c index c77ca2fc74..ec2345e9ab 100644 --- a/hw/misc/omap_clk.c +++ b/hw/misc/omap_clk.c @@ -30,174 +30,174 @@ struct clk { struct clk *parent; struct clk *child1; struct clk *sibling; -#define ALWAYS_ENABLED (1 << 0) -#define CLOCK_IN_OMAP310 (1 << 10) -#define CLOCK_IN_OMAP730 (1 << 11) -#define CLOCK_IN_OMAP1510 (1 << 12) -#define CLOCK_IN_OMAP16XX (1 << 13) -#define CLOCK_IN_OMAP242X (1 << 14) -#define CLOCK_IN_OMAP243X (1 << 15) -#define CLOCK_IN_OMAP343X (1 << 16) +#define ALWAYS_ENABLED (1 << 0) +#define CLOCK_IN_OMAP310 (1 << 10) +#define CLOCK_IN_OMAP730 (1 << 11) +#define CLOCK_IN_OMAP1510 (1 << 12) +#define CLOCK_IN_OMAP16XX (1 << 13) +#define CLOCK_IN_OMAP242X (1 << 14) +#define CLOCK_IN_OMAP243X (1 << 15) +#define CLOCK_IN_OMAP343X (1 << 16) uint32_t flags; int id; - int running; /* Is currently ticking */ - int enabled; /* Is enabled, regardless of its input clk */ - unsigned long rate; /* Current rate (if .running) */ - unsigned int divisor; /* Rate relative to input (if .enabled) */ - unsigned int multiplier; /* Rate relative to input (if .enabled) */ - qemu_irq users[16]; /* Who to notify on change */ - int usecount; /* Automatically idle when unused */ + int running; /* Is currently ticking */ + int enabled; /* Is enabled, regardless of its input clk */ + unsigned long rate; /* Current rate (if .running) */ + unsigned int divisor; /*g Rate relative to input (if .enabled) */ + unsigned int multiplier; /*g Rate relative to input (if .enabled) */ + qemu_irq users[16]; /* Who to notify on change */ + int usecount; /* Automatically idle when unused */ }; static struct clk xtal_osc12m = { - .name = "xtal_osc_12m", - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "xtal_osc_12m", + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk xtal_osc32k = { - .name = "xtal_osc_32k", - .rate = 32768, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "xtal_osc_32k", + .rate = 32768, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, }; static struct clk ck_ref = { - .name = "ck_ref", - .alias = "clkin", - .parent = &xtal_osc12m, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "ck_ref", + .alias = "clkin", + .parent = &xtal_osc12m, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; /* If a dpll is disabled it becomes a bypass, child clocks don't stop */ static struct clk dpll1 = { - .name = "dpll1", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "dpll1", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk dpll2 = { - .name = "dpll2", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name = "dpll2", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk dpll3 = { - .name = "dpll3", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name = "dpll3", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk dpll4 = { - .name = "dpll4", - .parent = &ck_ref, - .multiplier = 4, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "dpll4", + .parent = &ck_ref, + .multiplier = 4, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk apll = { - .name = "apll", - .parent = &ck_ref, - .multiplier = 48, - .divisor = 12, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "apll", + .parent = &ck_ref, + .multiplier = 48, + .divisor = 12, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk ck_48m = { - .name = "ck_48m", - .parent = &dpll4, /* either dpll4 or apll */ - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "ck_48m", + .parent = &dpll4, /*g either dpll4 or apll */ + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk ck_dpll1out = { - .name = "ck_dpll1out", - .parent = &dpll1, - .flags = CLOCK_IN_OMAP16XX, + .name = "ck_dpll1out", + .parent = &dpll1, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk sossi_ck = { - .name = "ck_sossi", - .parent = &ck_dpll1out, - .flags = CLOCK_IN_OMAP16XX, + .name = "ck_sossi", + .parent = &ck_dpll1out, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk clkm1 = { - .name = "clkm1", - .alias = "ck_gen1", - .parent = &dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "clkm1", + .alias = "ck_gen1", + .parent = &dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk clkm2 = { - .name = "clkm2", - .alias = "ck_gen2", - .parent = &dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "clkm2", + .alias = "ck_gen2", + .parent = &dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk clkm3 = { - .name = "clkm3", - .alias = "ck_gen3", - .parent = &dpll1, /* either dpll1 or ck_ref */ - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "clkm3", + .alias = "ck_gen3", + .parent = &dpll1, /*g either dpll1 or ck_ref */ + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk arm_ck = { - .name = "arm_ck", - .alias = "mpu_ck", - .parent = &clkm1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "arm_ck", + .alias = "mpu_ck", + .parent = &clkm1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk armper_ck = { - .name = "armper_ck", - .alias = "mpuper_ck", - .parent = &clkm1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "armper_ck", + .alias = "mpuper_ck", + .parent = &clkm1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk arm_gpio_ck = { - .name = "arm_gpio_ck", - .alias = "mpu_gpio_ck", - .parent = &clkm1, - .divisor = 1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name = "arm_gpio_ck", + .alias = "mpu_gpio_ck", + .parent = &clkm1, + .divisor = 1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; static struct clk armxor_ck = { - .name = "armxor_ck", - .alias = "mpuxor_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "armxor_ck", + .alias = "mpuxor_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk armtim_ck = { - .name = "armtim_ck", - .alias = "mputim_ck", - .parent = &ck_ref, /* either CLKIN or DPLL1 */ - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "armtim_ck", + .alias = "mputim_ck", + .parent = &ck_ref, /*g either CLKIN or DPLL1 */ + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk armwdt_ck = { - .name = "armwdt_ck", - .alias = "mpuwd_ck", - .parent = &clkm1, - .divisor = 14, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "armwdt_ck", + .alias = "mpuwd_ck", + .parent = &clkm1, + .divisor = 14, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk arminth_ck16xx = { - .name = "arminth_ck", - .parent = &arm_ck, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name = "arminth_ck", + .parent = &arm_ck, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, /* Note: On 16xx the frequency can be divided by 2 by programming * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * @@ -206,48 +206,48 @@ static struct clk arminth_ck16xx = { }; static struct clk dsp_ck = { - .name = "dsp_ck", - .parent = &clkm2, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name = "dsp_ck", + .parent = &clkm2, + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; static struct clk dspmmu_ck = { - .name = "dspmmu_ck", - .parent = &clkm2, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name = "dspmmu_ck", + .parent = &clkm2, + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; static struct clk dspper_ck = { - .name = "dspper_ck", - .parent = &clkm2, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name = "dspper_ck", + .parent = &clkm2, + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; static struct clk dspxor_ck = { - .name = "dspxor_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name = "dspxor_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; static struct clk dsptim_ck = { - .name = "dsptim_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name = "dsptim_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; static struct clk tc_ck = { - .name = "tc_ck", - .parent = &clkm3, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name = "tc_ck", + .parent = &clkm3, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk arminth_ck15xx = { - .name = "arminth_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name = "arminth_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, /* Note: On 1510 the frequency follows TC_CK * * 16xx version is in MPU clocks. @@ -256,606 +256,606 @@ static struct clk arminth_ck15xx = { static struct clk tipb_ck = { /* No-idle controlled by "tc_ck" */ - .name = "tipb_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .name = "tipb_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk l3_ocpi_ck = { /* No-idle controlled by "tc_ck" */ - .name = "l3_ocpi_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP16XX, + .name = "l3_ocpi_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk tc1_ck = { - .name = "tc1_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP16XX, + .name = "tc1_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk tc2_ck = { - .name = "tc2_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP16XX, + .name = "tc2_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk dma_ck = { /* No-idle controlled by "tc_ck" */ - .name = "dma_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .name = "dma_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk dma_lcdfree_ck = { - .name = "dma_lcdfree_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name = "dma_lcdfree_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; static struct clk api_ck = { - .name = "api_ck", - .alias = "mpui_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .name = "api_ck", + .alias = "mpui_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk lb_ck = { - .name = "lb_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name = "lb_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; static struct clk lbfree_ck = { - .name = "lbfree_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name = "lbfree_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; static struct clk hsab_ck = { - .name = "hsab_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name = "hsab_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; static struct clk rhea1_ck = { - .name = "rhea1_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name = "rhea1_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; static struct clk rhea2_ck = { - .name = "rhea2_ck", - .parent = &tc_ck, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .name = "rhea2_ck", + .parent = &tc_ck, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, }; static struct clk lcd_ck_16xx = { - .name = "lcd_ck", - .parent = &clkm3, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, + .name = "lcd_ck", + .parent = &clkm3, + .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, }; static struct clk lcd_ck_1510 = { - .name = "lcd_ck", - .parent = &clkm3, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .name = "lcd_ck", + .parent = &clkm3, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; static struct clk uart1_1510 = { - .name = "uart1_ck", + .name = "uart1_ck", /* Direct from ULPD, no real parent */ - .parent = &armper_ck, /* either armper_ck or dpll4 */ - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .parent = &armper_ck, /*g either armper_ck or dpll4 */ + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk uart1_16xx = { - .name = "uart1_ck", + .name = "uart1_ck", /* Direct from ULPD, no real parent */ - .parent = &armper_ck, - .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX, + .parent = &armper_ck, + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk uart2_ck = { - .name = "uart2_ck", + .name = "uart2_ck", /* Direct from ULPD, no real parent */ - .parent = &armper_ck, /* either armper_ck or dpll4 */ - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | + .parent = &armper_ck, /*g either armper_ck or dpll4 */ + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk uart3_1510 = { - .name = "uart3_ck", + .name = "uart3_ck", /* Direct from ULPD, no real parent */ - .parent = &armper_ck, /* either armper_ck or dpll4 */ - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .parent = &armper_ck, /*g either armper_ck or dpll4 */ + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, }; static struct clk uart3_16xx = { - .name = "uart3_ck", + .name = "uart3_ck", /* Direct from ULPD, no real parent */ - .parent = &armper_ck, - .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX, + .parent = &armper_ck, + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX, }; -static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */ - .name = "usb_clk0", - .alias = "usb.clko", +static struct clk usb_clk0 = { /*g 6 MHz output on W4_USB_CLK0 */ + .name = "usb_clk0", + .alias = "usb.clko", /* Direct from ULPD, no parent */ - .rate = 6000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .rate = 6000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk usb_hhc_ck1510 = { - .name = "usb_hhc_ck", + .name = "usb_hhc_ck", /* Direct from ULPD, no parent */ - .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, }; static struct clk usb_hhc_ck16xx = { - .name = "usb_hhc_ck", + .name = "usb_hhc_ck", /* Direct from ULPD, no parent */ - .rate = 48000000, + .rate = 48000000, /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ - .flags = CLOCK_IN_OMAP16XX, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk usb_w2fc_mclk = { - .name = "usb_w2fc_mclk", - .alias = "usb_w2fc_ck", - .parent = &ck_48m, - .rate = 48000000, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name = "usb_w2fc_mclk", + .alias = "usb_w2fc_ck", + .parent = &ck_48m, + .rate = 48000000, + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; static struct clk mclk_1510 = { - .name = "mclk", + .name = "mclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510, + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510, }; static struct clk bclk_310 = { - .name = "bt_mclk_out", /* Alias midi_mclk_out? */ - .parent = &armper_ck, - .flags = CLOCK_IN_OMAP310, + .name = "bt_mclk_out", /*g Alias midi_mclk_out? */ + .parent = &armper_ck, + .flags = CLOCK_IN_OMAP310, }; static struct clk mclk_310 = { - .name = "com_mclk_out", - .parent = &armper_ck, - .flags = CLOCK_IN_OMAP310, + .name = "com_mclk_out", + .parent = &armper_ck, + .flags = CLOCK_IN_OMAP310, }; static struct clk mclk_16xx = { - .name = "mclk", + .name = "mclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags = CLOCK_IN_OMAP16XX, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk bclk_1510 = { - .name = "bclk", + .name = "bclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510, + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510, }; static struct clk bclk_16xx = { - .name = "bclk", + .name = "bclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags = CLOCK_IN_OMAP16XX, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk mmc1_ck = { - .name = "mmc_ck", - .id = 1, + .name = "mmc_ck", + .id = 1, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck, /* either armper_ck or dpll4 */ - .rate = 48000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, + .parent = &armper_ck, /*g either armper_ck or dpll4 */ + .rate = 48000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, }; static struct clk mmc2_ck = { - .name = "mmc_ck", - .id = 2, + .name = "mmc_ck", + .id = 2, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck, - .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX, + .parent = &armper_ck, + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX, }; static struct clk cam_mclk = { - .name = "cam.mclk", - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, - .rate = 12000000, + .name = "cam.mclk", + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .rate = 12000000, }; static struct clk cam_exclk = { - .name = "cam.exclk", - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name = "cam.exclk", + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, /* Either 12M from cam.mclk or 48M from dpll4 */ - .parent = &cam_mclk, + .parent = &cam_mclk, }; static struct clk cam_lclk = { - .name = "cam.lclk", - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, + .name = "cam.lclk", + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, }; static struct clk i2c_fck = { - .name = "i2c_fck", - .id = 1, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name = "i2c_fck", + .id = 1, + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .parent = &armxor_ck, + .parent = &armxor_ck, }; static struct clk i2c_ick = { - .name = "i2c_ick", - .id = 1, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .parent = &armper_ck, + .name = "i2c_ick", + .id = 1, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .parent = &armper_ck, }; static struct clk clk32k = { - .name = "clk32-kHz", - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .name = "clk32-kHz", + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .parent = &xtal_osc32k, + .parent = &xtal_osc32k, }; static struct clk ref_clk = { - .name = "ref_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .rate = 12000000, /* 12 MHz or 13 MHz or 19.2 MHz */ - /*.parent = sys.xtalin */ + .name = "ref_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .rate = 12000000, /*g 12 MHz or 13 MHz or 19.2 MHz */ + /*.parent = sys.xtalin */ }; static struct clk apll_96m = { - .name = "apll_96m", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .rate = 96000000, - /*.parent = ref_clk */ + .name = "apll_96m", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .rate = 96000000, + /*.parent = ref_clk */ }; static struct clk apll_54m = { - .name = "apll_54m", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .rate = 54000000, - /*.parent = ref_clk */ + .name = "apll_54m", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .rate = 54000000, + /*.parent = ref_clk */ }; static struct clk sys_clk = { - .name = "sys_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .rate = 32768, - /*.parent = sys.xtalin */ + .name = "sys_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .rate = 32768, + /*.parent = sys.xtalin */ }; static struct clk sleep_clk = { - .name = "sleep_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .rate = 32768, - /*.parent = sys.xtalin */ + .name = "sleep_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .rate = 32768, + /*.parent = sys.xtalin */ }; static struct clk dpll_ck = { - .name = "dpll", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .parent = &ref_clk, + .name = "dpll", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .parent = &ref_clk, }; static struct clk dpll_x2_ck = { - .name = "dpll_x2", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .parent = &ref_clk, + .name = "dpll_x2", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .parent = &ref_clk, }; static struct clk wdt1_sys_clk = { - .name = "wdt1_sys_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, - .rate = 32768, - /*.parent = sys.xtalin */ + .name = "wdt1_sys_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, + .rate = 32768, + /*.parent = sys.xtalin */ }; static struct clk func_96m_clk = { - .name = "func_96m_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .divisor = 1, - .parent = &apll_96m, + .name = "func_96m_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .divisor = 1, + .parent = &apll_96m, }; static struct clk func_48m_clk = { - .name = "func_48m_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .divisor = 2, - .parent = &apll_96m, + .name = "func_48m_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .divisor = 2, + .parent = &apll_96m, }; static struct clk func_12m_clk = { - .name = "func_12m_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .divisor = 8, - .parent = &apll_96m, + .name = "func_12m_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .divisor = 8, + .parent = &apll_96m, }; static struct clk func_54m_clk = { - .name = "func_54m_clk", - .flags = CLOCK_IN_OMAP242X, - .divisor = 1, - .parent = &apll_54m, + .name = "func_54m_clk", + .flags = CLOCK_IN_OMAP242X, + .divisor = 1, + .parent = &apll_54m, }; static struct clk sys_clkout = { - .name = "clkout", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "clkout", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk sys_clkout2 = { - .name = "clkout2", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "clkout2", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_clk = { - .name = "core_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &dpll_x2_ck, /* Switchable between dpll_ck and clk32k */ + .name = "core_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &dpll_x2_ck, /*g Switchable between dpll_ck and clk32k */ }; static struct clk l3_clk = { - .name = "l3_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_clk, + .name = "l3_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_clk, }; static struct clk core_l4_iclk = { - .name = "core_l4_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &l3_clk, + .name = "core_l4_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &l3_clk, }; static struct clk wu_l4_iclk = { - .name = "wu_l4_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &l3_clk, + .name = "wu_l4_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &l3_clk, }; static struct clk core_l3_iclk = { - .name = "core_l3_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_clk, + .name = "core_l3_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_clk, }; static struct clk core_l4_usb_clk = { - .name = "core_l4_usb_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &l3_clk, + .name = "core_l4_usb_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &l3_clk, }; static struct clk wu_gpt1_clk = { - .name = "wu_gpt1_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "wu_gpt1_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk wu_32k_clk = { - .name = "wu_32k_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "wu_32k_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk uart1_fclk = { - .name = "uart1_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_48m_clk, + .name = "uart1_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_48m_clk, }; static struct clk uart1_iclk = { - .name = "uart1_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "uart1_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }; static struct clk uart2_fclk = { - .name = "uart2_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_48m_clk, + .name = "uart2_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_48m_clk, }; static struct clk uart2_iclk = { - .name = "uart2_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "uart2_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }; static struct clk uart3_fclk = { - .name = "uart3_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_48m_clk, + .name = "uart3_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_48m_clk, }; static struct clk uart3_iclk = { - .name = "uart3_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "uart3_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }; static struct clk mpu_fclk = { - .name = "mpu_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_clk, + .name = "mpu_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_clk, }; static struct clk mpu_iclk = { - .name = "mpu_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_clk, + .name = "mpu_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_clk, }; static struct clk int_m_fclk = { - .name = "int_m_fclk", - .alias = "mpu_intc_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_clk, + .name = "int_m_fclk", + .alias = "mpu_intc_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_clk, }; static struct clk int_m_iclk = { - .name = "int_m_iclk", - .alias = "mpu_intc_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_clk, + .name = "int_m_iclk", + .alias = "mpu_intc_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_clk, }; static struct clk core_gpt2_clk = { - .name = "core_gpt2_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt2_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt3_clk = { - .name = "core_gpt3_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt3_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt4_clk = { - .name = "core_gpt4_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt4_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt5_clk = { - .name = "core_gpt5_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt5_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt6_clk = { - .name = "core_gpt6_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt6_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt7_clk = { - .name = "core_gpt7_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt7_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt8_clk = { - .name = "core_gpt8_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt8_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt9_clk = { - .name = "core_gpt9_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt9_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt10_clk = { - .name = "core_gpt10_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt10_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt11_clk = { - .name = "core_gpt11_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt11_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk core_gpt12_clk = { - .name = "core_gpt12_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "core_gpt12_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }; static struct clk mcbsp1_clk = { - .name = "mcbsp1_cg", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .divisor = 2, - .parent = &func_96m_clk, + .name = "mcbsp1_cg", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .divisor = 2, + .parent = &func_96m_clk, }; static struct clk mcbsp2_clk = { - .name = "mcbsp2_cg", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .divisor = 2, - .parent = &func_96m_clk, + .name = "mcbsp2_cg", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .divisor = 2, + .parent = &func_96m_clk, }; static struct clk emul_clk = { - .name = "emul_ck", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_54m_clk, + .name = "emul_ck", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_54m_clk, }; static struct clk sdma_fclk = { - .name = "sdma_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &l3_clk, + .name = "sdma_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &l3_clk, }; static struct clk sdma_iclk = { - .name = "sdma_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */ + .name = "sdma_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */ }; static struct clk i2c1_fclk = { - .name = "i2c1.fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_12m_clk, - .divisor = 1, + .name = "i2c1.fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_12m_clk, + .divisor = 1, }; static struct clk i2c1_iclk = { - .name = "i2c1.iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "i2c1.iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }; static struct clk i2c2_fclk = { - .name = "i2c2.fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_12m_clk, - .divisor = 1, + .name = "i2c2.fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_12m_clk, + .divisor = 1, }; static struct clk i2c2_iclk = { - .name = "i2c2.iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "i2c2.iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }; static struct clk gpio_dbclk[5] = { { - .name = "gpio1_dbclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &wu_32k_clk, + .name = "gpio1_dbclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &wu_32k_clk, }, { - .name = "gpio2_dbclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &wu_32k_clk, + .name = "gpio2_dbclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &wu_32k_clk, }, { - .name = "gpio3_dbclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &wu_32k_clk, + .name = "gpio3_dbclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &wu_32k_clk, }, { - .name = "gpio4_dbclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &wu_32k_clk, + .name = "gpio4_dbclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &wu_32k_clk, }, { .name = "gpio5_dbclk", .flags = CLOCK_IN_OMAP243X, @@ -864,90 +864,90 @@ static struct clk gpio_dbclk[5] = { }; static struct clk gpio_iclk = { - .name = "gpio_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &wu_l4_iclk, + .name = "gpio_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &wu_l4_iclk, }; static struct clk mmc_fck = { - .name = "mmc_fclk", - .flags = CLOCK_IN_OMAP242X, - .parent = &func_96m_clk, + .name = "mmc_fclk", + .flags = CLOCK_IN_OMAP242X, + .parent = &func_96m_clk, }; static struct clk mmc_ick = { - .name = "mmc_iclk", - .flags = CLOCK_IN_OMAP242X, - .parent = &core_l4_iclk, + .name = "mmc_iclk", + .flags = CLOCK_IN_OMAP242X, + .parent = &core_l4_iclk, }; static struct clk spi_fclk[3] = { { - .name = "spi1_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_48m_clk, + .name = "spi1_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_48m_clk, }, { - .name = "spi2_fclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_48m_clk, + .name = "spi2_fclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_48m_clk, }, { - .name = "spi3_fclk", - .flags = CLOCK_IN_OMAP243X, - .parent = &func_48m_clk, + .name = "spi3_fclk", + .flags = CLOCK_IN_OMAP243X, + .parent = &func_48m_clk, }, }; static struct clk dss_clk[2] = { { - .name = "dss_clk1", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_clk, + .name = "dss_clk1", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_clk, }, { - .name = "dss_clk2", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &sys_clk, + .name = "dss_clk2", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &sys_clk, }, }; static struct clk dss_54m_clk = { - .name = "dss_54m_clk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &func_54m_clk, + .name = "dss_54m_clk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &func_54m_clk, }; static struct clk dss_l3_iclk = { - .name = "dss_l3_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l3_iclk, + .name = "dss_l3_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l3_iclk, }; static struct clk dss_l4_iclk = { - .name = "dss_l4_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "dss_l4_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }; static struct clk spi_iclk[3] = { { - .name = "spi1_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "spi1_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }, { - .name = "spi2_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "spi2_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }, { - .name = "spi3_iclk", - .flags = CLOCK_IN_OMAP243X, - .parent = &core_l4_iclk, + .name = "spi3_iclk", + .flags = CLOCK_IN_OMAP243X, + .parent = &core_l4_iclk, }, }; static struct clk omapctrl_clk = { - .name = "omapctrl_iclk", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .name = "omapctrl_iclk", + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, /* XXX Should be in WKUP domain */ - .parent = &core_l4_iclk, + .parent = &core_l4_iclk, }; static struct clk *onchip_clks[] = { @@ -1100,7 +1100,9 @@ void omap_clk_adduser(struct clk *clk, qemu_irq user) { qemu_irq *i; - for (i = clk->users; *i; i ++); + for (i = clk->users; *i; i++) { + ; + } *i = user; } @@ -1108,21 +1110,23 @@ struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name) { struct clk *i; - for (i = mpu->clks; i->name; i ++) - if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name))) + for (i = mpu->clks; i->name; i++) + if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name))) { return i; + } hw_error("%s: %s not found\n", __func__, name); } void omap_clk_get(struct clk *clk) { - clk->usecount ++; + clk->usecount++; } void omap_clk_put(struct clk *clk) { - if (!(clk->usecount --)) + if (!(clk->usecount--)) { hw_error("%s: %s is not in use\n", __func__, clk->name); + } } static void omap_clk_update(struct clk *clk) @@ -1131,19 +1135,22 @@ static void omap_clk_update(struct clk *clk) qemu_irq *user; struct clk *i; - if (clk->parent) + if (clk->parent) { parent = clk->parent->running; - else + } else { parent = 1; + } running = parent && (clk->enabled || ((clk->flags & ALWAYS_ENABLED) && clk->usecount)); if (clk->running != running) { clk->running = running; - for (user = clk->users; *user; user ++) + for (user = clk->users; *user; user++) { qemu_set_irq(*user, running); - for (i = clk->child1; i; i = i->sibling) + } + for (i = clk->child1; i; i = i->sibling) { omap_clk_update(i); + } } } @@ -1155,8 +1162,9 @@ static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate, clk->rate = muldiv64(rate, mult, div); if (clk->running) - for (user = clk->users; *user; user ++) + for (user = clk->users; *user; user++) { qemu_irq_raise(*user); + } for (i = clk->child1; i; i = i->sibling) omap_clk_rate_update_full(i, rate, div * i->divisor, mult * i->multiplier); @@ -1180,7 +1188,9 @@ void omap_clk_reparent(struct clk *clk, struct clk *parent) struct clk **p; if (clk->parent) { - for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling); + for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling) { + ; + } *p = clk->sibling; } @@ -1202,10 +1212,11 @@ void omap_clk_onoff(struct clk *clk, int on) void omap_clk_canidle(struct clk *clk, int can) { - if (can) + if (can) { omap_clk_put(clk); - else + } else { omap_clk_get(clk); + } } void omap_clk_setrate(struct clk *clk, int divide, int multiply) @@ -1226,27 +1237,29 @@ void omap_clk_init(struct omap_mpu_state_s *mpu) int count; int flag; - if (cpu_is_omap310(mpu)) + if (cpu_is_omap310(mpu)) { flag = CLOCK_IN_OMAP310; - else if (cpu_is_omap1510(mpu)) + } else if (cpu_is_omap1510(mpu)) { flag = CLOCK_IN_OMAP1510; - else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu)) + } else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu)) { flag = CLOCK_IN_OMAP242X; - else if (cpu_is_omap2430(mpu)) + } else if (cpu_is_omap2430(mpu)) { flag = CLOCK_IN_OMAP243X; - else if (cpu_is_omap3430(mpu)) + } else if (cpu_is_omap3430(mpu)) { flag = CLOCK_IN_OMAP243X; - else + } else { return; + } - for (i = onchip_clks, count = 0; *i; i ++) - if ((*i)->flags & flag) - count ++; + for (i = onchip_clks, count = 0; *i; i++) + if ((*i)->flags & flag) { + count++; + } mpu->clks = g_new0(struct clk, count + 1); - for (i = onchip_clks, j = mpu->clks; *i; i ++) + for (i = onchip_clks, j = mpu->clks; *i; i++) if ((*i)->flags & flag) { memcpy(j, *i, sizeof(struct clk)); - for (k = mpu->clks; k < j; k ++) + for (k = mpu->clks; k < j; k++) if (j->parent && !strcmp(j->parent->name, k->name)) { j->parent = k; j->sibling = k->child1; @@ -1258,9 +1271,9 @@ void omap_clk_init(struct omap_mpu_state_s *mpu) } j->divisor = j->divisor ?: 1; j->multiplier = j->multiplier ?: 1; - j ++; + j++; } - for (j = mpu->clks; count --; j ++) { + for (j = mpu->clks; count--; j++) { omap_clk_update(j); omap_clk_rate_update(j); } diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c index b7875489da..e0f5cea921 100644 --- a/hw/misc/omap_l4.c +++ b/hw/misc/omap_l4.c @@ -61,13 +61,13 @@ static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size) } switch (addr) { - case 0x00: /* COMPONENT */ + case 0x00: /* COMPONENT */ return s->component; - case 0x20: /* AGENT_CONTROL */ + case 0x20: /* AGENT_CONTROL */ return s->control; - case 0x28: /* AGENT_STATUS */ + case 0x28: /* AGENT_STATUS */ return s->status; } @@ -86,15 +86,16 @@ static void omap_l4ta_write(void *opaque, hwaddr addr, } switch (addr) { - case 0x00: /* COMPONENT */ - case 0x28: /* AGENT_STATUS */ + case 0x00: /* COMPONENT */ + case 0x28: /* AGENT_STATUS */ OMAP_RO_REG(addr); break; - case 0x20: /* AGENT_CONTROL */ + case 0x20: /* AGENT_CONTROL */ s->control = value & 0x01000700; - if (value & 1) /* OCP_RESET */ - s->status &= ~1; /* REQ_TIMEOUT */ + if (value & 1) { /* OCP_RESET */ + s->status &= ~1; /* REQ_TIMEOUT */ + } break; default: @@ -117,7 +118,7 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, struct omap_target_agent_s *ta = NULL; const struct omap_l4_agent_info_s *info = NULL; - for (i = 0; i < bus->ta_num; i ++) + for (i = 0; i < bus->ta_num; i++) if (agents[i].ta == cs) { ta = &bus->ta[i]; info = &agents[i]; @@ -134,7 +135,7 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); ta->status = 0x00000000; - ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ + ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ memory_region_init_io(&ta->iomem, NULL, &omap_l4ta_ops, ta, "omap.l4ta", omap_l4_region_size(ta, info->ta_region)); diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c index 6aa1b3ef7f..21d3ca8683 100644 --- a/hw/misc/omap_sdrc.c +++ b/hw/misc/omap_sdrc.c @@ -40,44 +40,44 @@ static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, unsigned size) } switch (addr) { - case 0x00: /* SDRC_REVISION */ + case 0x00: /* SDRC_REVISION */ return 0x20; - case 0x10: /* SDRC_SYSCONFIG */ + case 0x10: /* SDRC_SYSCONFIG */ return s->config; - case 0x14: /* SDRC_SYSSTATUS */ - return 1; /* RESETDONE */ - - case 0x40: /* SDRC_CS_CFG */ - case 0x44: /* SDRC_SHARING */ - case 0x48: /* SDRC_ERR_ADDR */ - case 0x4c: /* SDRC_ERR_TYPE */ - case 0x60: /* SDRC_DLLA_SCTRL */ - case 0x64: /* SDRC_DLLA_STATUS */ - case 0x68: /* SDRC_DLLB_CTRL */ - case 0x6c: /* SDRC_DLLB_STATUS */ - case 0x70: /* SDRC_POWER */ - case 0x80: /* SDRC_MCFG_0 */ - case 0x84: /* SDRC_MR_0 */ - case 0x88: /* SDRC_EMR1_0 */ - case 0x8c: /* SDRC_EMR2_0 */ - case 0x90: /* SDRC_EMR3_0 */ - case 0x94: /* SDRC_DCDL1_CTRL */ - case 0x98: /* SDRC_DCDL2_CTRL */ - case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ - case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ - case 0xa4: /* SDRC_RFR_CTRL_0 */ - case 0xa8: /* SDRC_MANUAL_0 */ - case 0xb0: /* SDRC_MCFG_1 */ - case 0xb4: /* SDRC_MR_1 */ - case 0xb8: /* SDRC_EMR1_1 */ - case 0xbc: /* SDRC_EMR2_1 */ - case 0xc0: /* SDRC_EMR3_1 */ - case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ - case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ - case 0xd4: /* SDRC_RFR_CTRL_1 */ - case 0xd8: /* SDRC_MANUAL_1 */ + case 0x14: /* SDRC_SYSSTATUS */ + return 1; /* RESETDONE */ + + case 0x40: /* SDRC_CS_CFG */ + case 0x44: /* SDRC_SHARING */ + case 0x48: /* SDRC_ERR_ADDR */ + case 0x4c: /* SDRC_ERR_TYPE */ + case 0x60: /* SDRC_DLLA_SCTRL */ + case 0x64: /* SDRC_DLLA_STATUS */ + case 0x68: /* SDRC_DLLB_CTRL */ + case 0x6c: /* SDRC_DLLB_STATUS */ + case 0x70: /* SDRC_POWER */ + case 0x80: /* SDRC_MCFG_0 */ + case 0x84: /* SDRC_MR_0 */ + case 0x88: /* SDRC_EMR1_0 */ + case 0x8c: /* SDRC_EMR2_0 */ + case 0x90: /* SDRC_EMR3_0 */ + case 0x94: /* SDRC_DCDL1_CTRL */ + case 0x98: /* SDRC_DCDL2_CTRL */ + case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ + case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ + case 0xa4: /* SDRC_RFR_CTRL_0 */ + case 0xa8: /* SDRC_MANUAL_0 */ + case 0xb0: /* SDRC_MCFG_1 */ + case 0xb4: /* SDRC_MR_1 */ + case 0xb8: /* SDRC_EMR1_1 */ + case 0xbc: /* SDRC_EMR2_1 */ + case 0xc0: /* SDRC_EMR3_1 */ + case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ + case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ + case 0xd4: /* SDRC_RFR_CTRL_1 */ + case 0xd8: /* SDRC_MANUAL_1 */ return 0x00; } @@ -96,49 +96,50 @@ static void omap_sdrc_write(void *opaque, hwaddr addr, } switch (addr) { - case 0x00: /* SDRC_REVISION */ - case 0x14: /* SDRC_SYSSTATUS */ - case 0x48: /* SDRC_ERR_ADDR */ - case 0x64: /* SDRC_DLLA_STATUS */ - case 0x6c: /* SDRC_DLLB_STATUS */ + case 0x00: /* SDRC_REVISION */ + case 0x14: /* SDRC_SYSSTATUS */ + case 0x48: /* SDRC_ERR_ADDR */ + case 0x64: /* SDRC_DLLA_STATUS */ + case 0x6c: /* SDRC_DLLB_STATUS */ OMAP_RO_REG(addr); return; - case 0x10: /* SDRC_SYSCONFIG */ + case 0x10: /* SDRC_SYSCONFIG */ if ((value >> 3) != 0x2) fprintf(stderr, "%s: bad SDRAM idle mode %i\n", __func__, (unsigned)value >> 3); - if (value & 2) + if (value & 2) { omap_sdrc_reset(s); + } s->config = value & 0x18; break; - case 0x40: /* SDRC_CS_CFG */ - case 0x44: /* SDRC_SHARING */ - case 0x4c: /* SDRC_ERR_TYPE */ - case 0x60: /* SDRC_DLLA_SCTRL */ - case 0x68: /* SDRC_DLLB_CTRL */ - case 0x70: /* SDRC_POWER */ - case 0x80: /* SDRC_MCFG_0 */ - case 0x84: /* SDRC_MR_0 */ - case 0x88: /* SDRC_EMR1_0 */ - case 0x8c: /* SDRC_EMR2_0 */ - case 0x90: /* SDRC_EMR3_0 */ - case 0x94: /* SDRC_DCDL1_CTRL */ - case 0x98: /* SDRC_DCDL2_CTRL */ - case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ - case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ - case 0xa4: /* SDRC_RFR_CTRL_0 */ - case 0xa8: /* SDRC_MANUAL_0 */ - case 0xb0: /* SDRC_MCFG_1 */ - case 0xb4: /* SDRC_MR_1 */ - case 0xb8: /* SDRC_EMR1_1 */ - case 0xbc: /* SDRC_EMR2_1 */ - case 0xc0: /* SDRC_EMR3_1 */ - case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ - case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ - case 0xd4: /* SDRC_RFR_CTRL_1 */ - case 0xd8: /* SDRC_MANUAL_1 */ + case 0x40: /* SDRC_CS_CFG */ + case 0x44: /* SDRC_SHARING */ + case 0x4c: /* SDRC_ERR_TYPE */ + case 0x60: /* SDRC_DLLA_SCTRL */ + case 0x68: /* SDRC_DLLB_CTRL */ + case 0x70: /* SDRC_POWER */ + case 0x80: /* SDRC_MCFG_0 */ + case 0x84: /* SDRC_MR_0 */ + case 0x88: /* SDRC_EMR1_0 */ + case 0x8c: /* SDRC_EMR2_0 */ + case 0x90: /* SDRC_EMR3_0 */ + case 0x94: /* SDRC_DCDL1_CTRL */ + case 0x98: /* SDRC_DCDL2_CTRL */ + case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ + case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ + case 0xa4: /* SDRC_RFR_CTRL_0 */ + case 0xa8: /* SDRC_MANUAL_0 */ + case 0xb0: /* SDRC_MCFG_1 */ + case 0xb4: /* SDRC_MR_1 */ + case 0xb8: /* SDRC_EMR1_1 */ + case 0xbc: /* SDRC_EMR2_1 */ + case 0xc0: /* SDRC_EMR3_1 */ + case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ + case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ + case 0xd4: /* SDRC_RFR_CTRL_1 */ + case 0xd8: /* SDRC_MANUAL_1 */ break; default: diff --git a/hw/misc/omap_tap.c b/hw/misc/omap_tap.c index 4d7fb7d85f..daa15696ee 100644 --- a/hw/misc/omap_tap.c +++ b/hw/misc/omap_tap.c @@ -32,25 +32,25 @@ static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size) } switch (addr) { - case 0x204: /* IDCODE_reg */ + case 0x204: /* IDCODE_reg */ switch (s->mpu_model) { case omap2420: case omap2422: case omap2423: - return 0x5b5d902f; /* ES 2.2 */ + return 0x5b5d902f; /* ES 2.2 */ case omap2430: - return 0x5b68a02f; /* ES 2.2 */ + return 0x5b68a02f; /* ES 2.2 */ case omap3430: - return 0x1b7ae02f; /* ES 2 */ + return 0x1b7ae02f; /* ES 2 */ default: hw_error("%s: Bad mpu model\n", __func__); } - case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ - case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ + case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ + case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ switch (s->mpu_model) { case omap2420: - return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ + return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ case omap2422: return 0x000400f0; case omap2423: @@ -68,22 +68,22 @@ static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size) case omap2420: case omap2422: case omap2423: - return 0xcafeb5d9; /* ES 2.2 */ + return 0xcafeb5d9; /* ES 2.2 */ case omap2430: - return 0xcafeb68a; /* ES 2.2 */ + return 0xcafeb68a; /* ES 2.2 */ case omap3430: - return 0xcafeb7ae; /* ES 2 */ + return 0xcafeb7ae; /* ES 2 */ default: hw_error("%s: Bad mpu model\n", __func__); } - case 0x218: /* DIE_ID_reg */ + case 0x218: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); - case 0x21c: /* DIE_ID_reg */ + case 0x21c: /* DIE_ID_reg */ return 0x54 << 24; - case 0x220: /* DIE_ID_reg */ + case 0x220: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); - case 0x224: /* DIE_ID_reg */ + case 0x224: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); } diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index edd3cf2a1e..848e42f076 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -104,11 +104,11 @@ static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) } typedef enum { - sd_nore = 0, /* no response */ - sd_r1, /* normal response command */ - sd_r2, /* CID, CSD registers */ - sd_r3, /* OCR register */ - sd_r6 = 6, /* Published RCA response */ + sd_nore = 0, /* no response */ + sd_r1, /* normal response command */ + sd_r2, /* CID, CSD registers */ + sd_r3, /* OCR register */ + sd_r6 = 6, /* Published RCA response */ sd_r1b = -1, } sd_rsp_type_t; @@ -125,8 +125,9 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, return; } - if (resptype == sd_r1 && busy) + if (resptype == sd_r1 && busy) { resptype = sd_r1b; + } if (type == sd_adtc) { host->fifo_start = 0; @@ -164,8 +165,9 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | CARD_ECC_FAILED | CC_ERROR | SD_ERROR | CID_CSD_OVERWRITE; - if (host->sdio & (1 << 13)) + if (host->sdio & (1 << 13)) { mask |= AKE_SEQ_ERROR; + } rspstatus = ldl_be_p(response); break; @@ -185,10 +187,11 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, rsplen = 4; rspstatus = ldl_be_p(response); - if (rspstatus & 0x80000000) + if (rspstatus & 0x80000000) { host->status &= 0xe000; - else + } else { host->status |= 0x1000; + } break; case sd_r6: @@ -202,35 +205,39 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, rspstatus = (response[2] << 8) | (response[3] << 0); } - if (rspstatus & mask) + if (rspstatus & mask) { host->status |= 0x4000; - else + } else { host->status &= 0xb000; + } if (rsplen) - for (rsplen = 0; rsplen < 8; rsplen ++) + for (rsplen = 0; rsplen < 8; rsplen++) host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | (response[(rsplen << 1) | 0] << 8); - if (timeout) + if (timeout) { host->status |= 0x0080; - else if (cmd == 12) - host->status |= 0x0005; /* Makes it more real */ - else + } else if (cmd == 12) { + host->status |= 0x0005; /* Makes it more real */ + } else { host->status |= 0x0001; + } } static void omap_mmc_transfer(struct omap_mmc_s *host) { uint8_t value; - if (!host->transfer) + if (!host->transfer) { return; + } while (1) { if (host->ddir) { - if (host->fifo_len > host->af_level) + if (host->fifo_len > host->af_level) { break; + } value = sd_read_byte(host->card); host->fifo[(host->fifo_start + host->fifo_len) & 31] = value; @@ -238,29 +245,30 @@ static void omap_mmc_transfer(struct omap_mmc_s *host) value = sd_read_byte(host->card); host->fifo[(host->fifo_start + host->fifo_len) & 31] |= value << 8; - host->blen_counter --; + host->blen_counter--; } - host->fifo_len ++; + host->fifo_len++; } else { - if (!host->fifo_len) + if (!host->fifo_len) { break; + } value = host->fifo[host->fifo_start] & 0xff; sd_write_byte(host->card, value); if (-- host->blen_counter) { value = host->fifo[host->fifo_start] >> 8; sd_write_byte(host->card, value); - host->blen_counter --; + host->blen_counter--; } - host->fifo_start ++; - host->fifo_len --; + host->fifo_start++; + host->fifo_len--; host->fifo_start &= 31; } if (host->blen_counter == 0) { - host->nblk_counter --; + host->nblk_counter--; host->blen_counter = host->blen; if (host->nblk_counter == 0) { @@ -331,82 +339,82 @@ static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size) } switch (offset) { - case 0x00: /* MMC_CMD */ + case 0x00: /* MMC_CMD */ return s->last_cmd; - case 0x04: /* MMC_ARGL */ + case 0x04: /* MMC_ARGL */ return s->arg & 0x0000ffff; - case 0x08: /* MMC_ARGH */ + case 0x08: /* MMC_ARGH */ return s->arg >> 16; - case 0x0c: /* MMC_CON */ - return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | + case 0x0c: /* MMC_CON */ + return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | (s->be << 10) | s->clkdiv; - case 0x10: /* MMC_STAT */ + case 0x10: /* MMC_STAT */ return s->status; - case 0x14: /* MMC_IE */ + case 0x14: /* MMC_IE */ return s->mask; - case 0x18: /* MMC_CTO */ + case 0x18: /* MMC_CTO */ return s->cto; - case 0x1c: /* MMC_DTO */ + case 0x1c: /* MMC_DTO */ return s->dto; - case 0x20: /* MMC_DATA */ + case 0x20: /* MMC_DATA */ /* TODO: support 8-bit access */ i = s->fifo[s->fifo_start]; if (s->fifo_len == 0) { printf("MMC: FIFO underrun\n"); return i; } - s->fifo_start ++; - s->fifo_len --; + s->fifo_start++; + s->fifo_len--; s->fifo_start &= 31; omap_mmc_transfer(s); omap_mmc_fifolevel_update(s); omap_mmc_interrupts_update(s); return i; - case 0x24: /* MMC_BLEN */ + case 0x24: /* MMC_BLEN */ return s->blen_counter; - case 0x28: /* MMC_NBLK */ + case 0x28: /* MMC_NBLK */ return s->nblk_counter; - case 0x2c: /* MMC_BUF */ + case 0x2c: /* MMC_BUF */ return (s->rx_dma << 15) | (s->af_level << 8) | (s->tx_dma << 7) | s->ae_level; - case 0x30: /* MMC_SPI */ + case 0x30: /* MMC_SPI */ return 0x0000; - case 0x34: /* MMC_SDIO */ + case 0x34: /* MMC_SDIO */ return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; - case 0x38: /* MMC_SYST */ + case 0x38: /* MMC_SYST */ return 0x0000; - case 0x3c: /* MMC_REV */ + case 0x3c: /* MMC_REV */ return s->rev; - case 0x40: /* MMC_RSP0 */ - case 0x44: /* MMC_RSP1 */ - case 0x48: /* MMC_RSP2 */ - case 0x4c: /* MMC_RSP3 */ - case 0x50: /* MMC_RSP4 */ - case 0x54: /* MMC_RSP5 */ - case 0x58: /* MMC_RSP6 */ - case 0x5c: /* MMC_RSP7 */ + case 0x40: /* MMC_RSP0 */ + case 0x44: /* MMC_RSP1 */ + case 0x48: /* MMC_RSP2 */ + case 0x4c: /* MMC_RSP3 */ + case 0x50: /* MMC_RSP4 */ + case 0x54: /* MMC_RSP5 */ + case 0x58: /* MMC_RSP6 */ + case 0x5c: /* MMC_RSP7 */ return s->rsp[(offset - 0x40) >> 2]; /* OMAP2-specific */ - case 0x60: /* MMC_IOSR */ - case 0x64: /* MMC_SYSC */ + case 0x60: /* MMC_IOSR */ + case 0x64: /* MMC_SYSC */ return 0; - case 0x68: /* MMC_SYSS */ - return 1; /* RSTD */ + case 0x68: /* MMC_SYSS */ + return 1; /* RSTD */ } OMAP_BAD_REG(offset); @@ -425,13 +433,15 @@ static void omap_mmc_write(void *opaque, hwaddr offset, } switch (offset) { - case 0x00: /* MMC_CMD */ - if (!s->enable) + case 0x00: /* MMC_CMD */ + if (!s->enable) { break; + } s->last_cmd = value; - for (i = 0; i < 8; i ++) + for (i = 0; i < 8; i++) { s->rsp[i] = 0x0000; + } omap_mmc_command(s, value & 63, (value >> 15) & 1, (sd_cmd_type_t) ((value >> 12) & 3), (value >> 11) & 1, @@ -440,17 +450,17 @@ static void omap_mmc_write(void *opaque, hwaddr offset, omap_mmc_update(s); break; - case 0x04: /* MMC_ARGL */ + case 0x04: /* MMC_ARGL */ s->arg &= 0xffff0000; s->arg |= 0x0000ffff & value; break; - case 0x08: /* MMC_ARGH */ + case 0x08: /* MMC_ARGH */ s->arg &= 0x0000ffff; s->arg |= value << 16; break; - case 0x0c: /* MMC_CON */ + case 0x0c: /* MMC_CON */ s->dw = (value >> 15) & 1; s->mode = (value >> 12) & 3; s->enable = (value >> 11) & 1; @@ -464,101 +474,109 @@ static void omap_mmc_write(void *opaque, hwaddr offset, qemu_log_mask(LOG_UNIMP, "omap_mmc_wr: Big Endian not implemented\n"); } - if (s->dw != 0 && s->lines < 4) + if (s->dw != 0 && s->lines < 4) { printf("4-bit SD bus enabled\n"); - if (!s->enable) + } + if (!s->enable) { omap_mmc_pseudo_reset(s); + } break; - case 0x10: /* MMC_STAT */ + case 0x10: /* MMC_STAT */ s->status &= ~value; omap_mmc_interrupts_update(s); break; - case 0x14: /* MMC_IE */ + case 0x14: /* MMC_IE */ s->mask = value & 0x7fff; omap_mmc_interrupts_update(s); break; - case 0x18: /* MMC_CTO */ + case 0x18: /* MMC_CTO */ s->cto = value & 0xff; - if (s->cto > 0xfd && s->rev <= 1) + if (s->cto > 0xfd && s->rev <= 1) { printf("MMC: CTO of 0xff and 0xfe cannot be used!\n"); + } break; - case 0x1c: /* MMC_DTO */ + case 0x1c: /* MMC_DTO */ s->dto = value & 0xffff; break; - case 0x20: /* MMC_DATA */ + case 0x20: /* MMC_DATA */ /* TODO: support 8-bit access */ - if (s->fifo_len == 32) + if (s->fifo_len == 32) { break; + } s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; - s->fifo_len ++; + s->fifo_len++; omap_mmc_transfer(s); omap_mmc_fifolevel_update(s); omap_mmc_interrupts_update(s); break; - case 0x24: /* MMC_BLEN */ + case 0x24: /* MMC_BLEN */ s->blen = (value & 0x07ff) + 1; s->blen_counter = s->blen; break; - case 0x28: /* MMC_NBLK */ + case 0x28: /* MMC_NBLK */ s->nblk = (value & 0x07ff) + 1; s->nblk_counter = s->nblk; s->blen_counter = s->blen; break; - case 0x2c: /* MMC_BUF */ + case 0x2c: /* MMC_BUF */ s->rx_dma = (value >> 15) & 1; s->af_level = (value >> 8) & 0x1f; s->tx_dma = (value >> 7) & 1; s->ae_level = value & 0x1f; - if (s->rx_dma) + if (s->rx_dma) { s->status &= 0xfbff; - if (s->tx_dma) + } + if (s->tx_dma) { s->status &= 0xf7ff; + } omap_mmc_fifolevel_update(s); omap_mmc_interrupts_update(s); break; /* SPI, SDIO and TEST modes unimplemented */ - case 0x30: /* MMC_SPI (OMAP1 only) */ + case 0x30: /* MMC_SPI (OMAP1 only) */ break; - case 0x34: /* MMC_SDIO */ + case 0x34: /* MMC_SDIO */ s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); s->cdet_wakeup = (value >> 9) & 1; s->cdet_enable = (value >> 2) & 1; break; - case 0x38: /* MMC_SYST */ + case 0x38: /* MMC_SYST */ break; - case 0x3c: /* MMC_REV */ - case 0x40: /* MMC_RSP0 */ - case 0x44: /* MMC_RSP1 */ - case 0x48: /* MMC_RSP2 */ - case 0x4c: /* MMC_RSP3 */ - case 0x50: /* MMC_RSP4 */ - case 0x54: /* MMC_RSP5 */ - case 0x58: /* MMC_RSP6 */ - case 0x5c: /* MMC_RSP7 */ + case 0x3c: /* MMC_REV */ + case 0x40: /* MMC_RSP0 */ + case 0x44: /* MMC_RSP1 */ + case 0x48: /* MMC_RSP2 */ + case 0x4c: /* MMC_RSP3 */ + case 0x50: /* MMC_RSP4 */ + case 0x54: /* MMC_RSP5 */ + case 0x58: /* MMC_RSP6 */ + case 0x5c: /* MMC_RSP7 */ OMAP_RO_REG(offset); break; /* OMAP2-specific */ - case 0x60: /* MMC_IOSR */ - if (value & 0xf) + case 0x60: /* MMC_IOSR */ + if (value & 0xf) { printf("MMC: SDIO bits used!\n"); + } break; - case 0x64: /* MMC_SYSC */ - if (value & (1 << 2)) /* SRTS */ + case 0x64: /* MMC_SYSC */ + if (value & (1 << 2)) { /* SRTS */ omap_mmc_reset(s); + } break; - case 0x68: /* MMC_SYSS */ + case 0x68: /* MMC_SYSS */ OMAP_RO_REG(offset); break; @@ -601,7 +619,7 @@ struct omap_mmc_s *omap_mmc_init(hwaddr base, s->irq = irq; s->dma = dma; s->clk = clk; - s->lines = 1; /* TODO: needs to be settable per-board */ + s->lines = 1; /* TODO: needs to be settable per-board */ s->rev = 1; memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800); diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c index 82529708c8..4fd17da95b 100644 --- a/hw/sd/pxa2xx_mmci.c +++ b/hw/sd/pxa2xx_mmci.c @@ -113,55 +113,55 @@ static const VMStateDescription vmstate_pxa2xx_mmci = { } }; -#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ -#define MMC_STAT 0x04 /* MMC Status register */ -#define MMC_CLKRT 0x08 /* MMC Clock Rate register */ -#define MMC_SPI 0x0c /* MMC SPI Mode register */ -#define MMC_CMDAT 0x10 /* MMC Command/Data register */ -#define MMC_RESTO 0x14 /* MMC Response Time-Out register */ -#define MMC_RDTO 0x18 /* MMC Read Time-Out register */ -#define MMC_BLKLEN 0x1c /* MMC Block Length register */ -#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */ -#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */ -#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */ -#define MMC_I_REG 0x2c /* MMC Interrupt Request register */ -#define MMC_CMD 0x30 /* MMC Command register */ -#define MMC_ARGH 0x34 /* MMC Argument High register */ -#define MMC_ARGL 0x38 /* MMC Argument Low register */ -#define MMC_RES 0x3c /* MMC Response FIFO */ -#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */ -#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */ -#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */ -#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */ +#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ +#define MMC_STAT 0x04 /* MMC Status register */ +#define MMC_CLKRT 0x08 /* MMC Clock Rate register */ +#define MMC_SPI 0x0c /* MMC SPI Mode register */ +#define MMC_CMDAT 0x10 /* MMC Command/Data register */ +#define MMC_RESTO 0x14 /* MMC Response Time-Out register */ +#define MMC_RDTO 0x18 /* MMC Read Time-Out register */ +#define MMC_BLKLEN 0x1c /* MMC Block Length register */ +#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */ +#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */ +#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */ +#define MMC_I_REG 0x2c /* MMC Interrupt Request register */ +#define MMC_CMD 0x30 /* MMC Command register */ +#define MMC_ARGH 0x34 /* MMC Argument High register */ +#define MMC_ARGL 0x38 /* MMC Argument Low register */ +#define MMC_RES 0x3c /* MMC Response FIFO */ +#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */ +#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */ +#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */ +#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */ /* Bitfield masks */ -#define STRPCL_STOP_CLK (1 << 0) -#define STRPCL_STRT_CLK (1 << 1) -#define STAT_TOUT_RES (1 << 1) -#define STAT_CLK_EN (1 << 8) -#define STAT_DATA_DONE (1 << 11) -#define STAT_PRG_DONE (1 << 12) -#define STAT_END_CMDRES (1 << 13) -#define SPI_SPI_MODE (1 << 0) -#define CMDAT_RES_TYPE (3 << 0) -#define CMDAT_DATA_EN (1 << 2) -#define CMDAT_WR_RD (1 << 3) -#define CMDAT_DMA_EN (1 << 7) -#define CMDAT_STOP_TRAN (1 << 10) -#define INT_DATA_DONE (1 << 0) -#define INT_PRG_DONE (1 << 1) -#define INT_END_CMD (1 << 2) -#define INT_STOP_CMD (1 << 3) -#define INT_CLK_OFF (1 << 4) -#define INT_RXFIFO_REQ (1 << 5) -#define INT_TXFIFO_REQ (1 << 6) -#define INT_TINT (1 << 7) -#define INT_DAT_ERR (1 << 8) -#define INT_RES_ERR (1 << 9) -#define INT_RD_STALLED (1 << 10) -#define INT_SDIO_INT (1 << 11) -#define INT_SDIO_SACK (1 << 12) -#define PRTBUF_PRT_BUF (1 << 0) +#define STRPCL_STOP_CLK (1 << 0) +#define STRPCL_STRT_CLK (1 << 1) +#define STAT_TOUT_RES (1 << 1) +#define STAT_CLK_EN (1 << 8) +#define STAT_DATA_DONE (1 << 11) +#define STAT_PRG_DONE (1 << 12) +#define STAT_END_CMDRES (1 << 13) +#define SPI_SPI_MODE (1 << 0) +#define CMDAT_RES_TYPE (3 << 0) +#define CMDAT_DATA_EN (1 << 2) +#define CMDAT_WR_RD (1 << 3) +#define CMDAT_DMA_EN (1 << 7) +#define CMDAT_STOP_TRAN (1 << 10) +#define INT_DATA_DONE (1 << 0) +#define INT_PRG_DONE (1 << 1) +#define INT_END_CMD (1 << 2) +#define INT_STOP_CMD (1 << 3) +#define INT_CLK_OFF (1 << 4) +#define INT_RXFIFO_REQ (1 << 5) +#define INT_TXFIFO_REQ (1 << 6) +#define INT_TINT (1 << 7) +#define INT_DAT_ERR (1 << 8) +#define INT_RES_ERR (1 << 9) +#define INT_RD_STALLED (1 << 10) +#define INT_SDIO_INT (1 << 11) +#define INT_SDIO_SACK (1 << 12) +#define PRTBUF_PRT_BUF (1 << 0) /* Route internal interrupt lines to the global IC and DMA */ static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s) @@ -179,23 +179,25 @@ static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s) static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s) { - if (!s->active) + if (!s->active) { return; + } if (s->cmdat & CMDAT_WR_RD) { while (s->bytesleft && s->tx_len) { sdbus_write_byte(&s->sdbus, s->tx_fifo[s->tx_start++]); s->tx_start &= 0x1f; - s->tx_len --; - s->bytesleft --; + s->tx_len--; + s->bytesleft--; } - if (s->bytesleft) + if (s->bytesleft) { s->intreq |= INT_TXFIFO_REQ; + } } else while (s->bytesleft && s->rx_len < 32) { - s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] = + s->rx_fifo[(s->rx_start + (s->rx_len++)) & 0x1f] = sdbus_read_byte(&s->sdbus); - s->bytesleft --; + s->bytesleft--; s->intreq |= INT_RXFIFO_REQ; } @@ -226,44 +228,50 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s) request.cmd = s->cmd; request.arg = s->arg; - request.crc = 0; /* FIXME */ + request.crc = 0; /* FIXME */ rsplen = sdbus_do_command(&s->sdbus, &request, response); s->intreq |= INT_END_CMD; memset(s->resp_fifo, 0, sizeof(s->resp_fifo)); switch (s->cmdat & CMDAT_RES_TYPE) { -#define PXAMMCI_RESP(wd, value0, value1) \ - s->resp_fifo[(wd) + 0] |= (value0); \ - s->resp_fifo[(wd) + 1] |= (value1) << 8; - case 0: /* No response */ +#define PXAMMCI_RESP(wd, value0, value1) \ + do { \ + s->resp_fifo[(wd) + 0] = (value0); \ + s->resp_fifo[(wd) + 1] = (value1); \ + } while (0) + case 0: /* No response */ goto complete; - case 1: /* R1, R4, R5 or R6 */ - if (rsplen < 4) + case 1: /* R1, R4, R5 or R6 */ + if (rsplen < 4) { goto timeout; + } goto complete; - case 2: /* R2 */ - if (rsplen < 16) + case 2: /* R2 */ + if (rsplen < 16) { goto timeout; + } goto complete; - case 3: /* R3 */ - if (rsplen < 4) + case 3: /* R3 */ + if (rsplen < 4) { goto timeout; + } goto complete; complete: - for (i = 0; rsplen > 0; i ++, rsplen -= 2) { + for (i = 0; rsplen > 0; i++, rsplen -= 2) { PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]); } s->status |= STAT_END_CMDRES; - if (!(s->cmdat & CMDAT_DATA_EN)) + if (!(s->cmdat & CMDAT_DATA_EN)) { s->active = 0; - else + } else { s->bytesleft = s->numblk * s->blklen; + } s->resp_len = 0; break; @@ -333,7 +341,7 @@ static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size) while (size-- && s->rx_len) { ret |= s->rx_fifo[s->rx_start++] << (size << 3); s->rx_start &= 0x1f; - s->rx_len --; + s->rx_len--; } s->intreq &= ~INT_RXFIFO_REQ; pxa2xx_mmci_fifo_update(s); @@ -399,8 +407,9 @@ static void pxa2xx_mmci_write(void *opaque, if (!(value & CMDAT_STOP_TRAN)) { s->status &= STAT_CLK_EN; - if (s->status & STAT_CLK_EN) + if (s->status & STAT_CLK_EN) { pxa2xx_mmci_wakequeues(s); + } } pxa2xx_mmci_int_update(s); @@ -451,7 +460,7 @@ static void pxa2xx_mmci_write(void *opaque, case MMC_TXFIFO: while (size-- && s->tx_len < 0x20) - s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] = + s->tx_fifo[(s->tx_start + (s->tx_len++)) & 0x1f] = (value >> (size << 3)) & 0xff; s->intreq &= ~INT_TXFIFO_REQ; pxa2xx_mmci_fifo_update(s); diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c index 34e6af7aff..078ce294eb 100644 --- a/hw/timer/omap_gptimer.c +++ b/hw/timer/omap_gptimer.c @@ -69,27 +69,29 @@ struct omap_gp_timer_s { uint32_t match_val; int capt_num; - uint16_t writeh; /* LSB */ - uint16_t readh; /* MSB */ + uint16_t writeh; /* LSB */ + uint16_t readh; /* MSB */ }; -#define GPT_TCAR_IT (1 << 2) -#define GPT_OVF_IT (1 << 1) -#define GPT_MAT_IT (1 << 0) +#define GPT_TCAR_IT (1 << 2) +#define GPT_OVF_IT (1 << 1) +#define GPT_MAT_IT (1 << 0) static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it) { if (timer->it_ena & it) { - if (!timer->status) + if (!timer->status) { qemu_irq_raise(timer->irq); + } timer->status |= it; /* Or are the status bits set even when masked? * i.e. is masking applied before or after the status register? */ } - if (timer->wu_ena & it) + if (timer->wu_ena & it) { qemu_irq_pulse(timer->wkup); + } } static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level) @@ -108,10 +110,11 @@ static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer) distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; distance = muldiv64(distance, timer->rate, timer->ticks_per_sec); - if (distance >= 0xffffffff - timer->val) + if (distance >= 0xffffffff - timer->val) { return 0xffffffff; - else + } else { return timer->val + distance; + } } else return timer->val; } @@ -148,13 +151,14 @@ static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer) static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) { - if (timer->pt) + if (timer->pt) { /* TODO in overflow-and-match mode if the first event to * occur is the match, don't toggle. */ omap_gp_timer_out(timer, !timer->out_val); - else + } else { /* TODO inverted pulse on timer->out_val == 1? */ qemu_irq_pulse(timer->out); + } } static void omap_gp_timer_tick(void *opaque) @@ -181,8 +185,9 @@ static void omap_gp_timer_match(void *opaque) { struct omap_gp_timer_s *timer = opaque; - if (timer->trigger == gpt_trigger_both) + if (timer->trigger == gpt_trigger_both) { omap_gp_timer_trigger(timer); + } omap_gp_timer_intr(timer, GPT_MAT_IT); } @@ -212,8 +217,9 @@ static void omap_gp_timer_input(void *opaque, int line, int on) if (s->inout && trigger && s->capt_num < 2) { s->capture_val[s->capt_num] = omap_gp_timer_read(s); - if (s->capt2 == s->capt_num ++) + if (s->capt2 == s->capt_num++) { omap_gp_timer_intr(s, GPT_TCAR_IT); + } } } @@ -265,26 +271,26 @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr) struct omap_gp_timer_s *s = opaque; switch (addr) { - case 0x00: /* TIDR */ + case 0x00: /* TIDR */ return 0x21; - case 0x10: /* TIOCP_CFG */ + case 0x10: /* TIOCP_CFG */ return s->config; - case 0x14: /* TISTAT */ + case 0x14: /* TISTAT */ /* ??? When's this bit reset? */ - return 1; /* RESETDONE */ + return 1; /* RESETDONE */ - case 0x18: /* TISR */ + case 0x18: /* TISR */ return s->status; - case 0x1c: /* TIER */ + case 0x1c: /* TIER */ return s->it_ena; - case 0x20: /* TWER */ + case 0x20: /* TWER */ return s->wu_ena; - case 0x24: /* TCLR */ + case 0x24: /* TCLR */ return (s->inout << 14) | (s->capt2 << 13) | (s->pt << 12) | @@ -297,28 +303,28 @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr) (s->ar << 1) | (s->st << 0); - case 0x28: /* TCRR */ + case 0x28: /* TCRR */ return omap_gp_timer_read(s); - case 0x2c: /* TLDR */ + case 0x2c: /* TLDR */ return s->load_val; - case 0x30: /* TTGR */ + case 0x30: /* TTGR */ return 0xffffffff; - case 0x34: /* TWPS */ - return 0x00000000; /* No posted writes pending. */ + case 0x34: /* TWPS */ + return 0x00000000; /* No posted writes pending. */ - case 0x38: /* TMAR */ + case 0x38: /* TMAR */ return s->match_val; - case 0x3c: /* TCAR1 */ + case 0x3c: /* TCAR1 */ return s->capture_val[0]; - case 0x40: /* TSICR */ + case 0x40: /* TSICR */ return s->posted << 2; - case 0x44: /* TCAR2 */ + case 0x44: /* TCAR2 */ return s->capture_val[1]; } @@ -345,47 +351,54 @@ static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value) struct omap_gp_timer_s *s = opaque; switch (addr) { - case 0x00: /* TIDR */ - case 0x14: /* TISTAT */ - case 0x34: /* TWPS */ - case 0x3c: /* TCAR1 */ - case 0x44: /* TCAR2 */ + case 0x00: /* TIDR */ + case 0x14: /* TISTAT */ + case 0x34: /* TWPS */ + case 0x3c: /* TCAR1 */ + case 0x44: /* TCAR2 */ OMAP_RO_REG(addr); break; - case 0x10: /* TIOCP_CFG */ + case 0x10: /* TIOCP_CFG */ s->config = value & 0x33d; - if (((value >> 3) & 3) == 3) /* IDLEMODE */ + if (((value >> 3) & 3) == 3) { /* IDLEMODE */ fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n", __func__); - if (value & 2) /* SOFTRESET */ + } + if (value & 2) /* SOFTRESET */ omap_gp_timer_reset(s); break; - case 0x18: /* TISR */ - if (value & GPT_TCAR_IT) + case 0x18: /* TISR */ + if (value & GPT_TCAR_IT) { s->capt_num = 0; - if (s->status && !(s->status &= ~value)) - qemu_irq_lower(s->irq); + } + if (s->status) { + s->status &= ~value; + if (!s->status) { + qemu_irq_lower(s->irq); + } + } break; - case 0x1c: /* TIER */ + case 0x1c: /* TIER */ s->it_ena = value & 7; break; - case 0x20: /* TWER */ + case 0x20: /* TWER */ s->wu_ena = value & 7; break; - case 0x24: /* TCLR */ + case 0x24: /* TCLR */ omap_gp_timer_sync(s); s->inout = (value >> 14) & 1; s->capt2 = (value >> 13) & 1; s->pt = (value >> 12) & 1; s->trigger = (value >> 10) & 3; if (s->capture == gpt_capture_none && - ((value >> 8) & 3) != gpt_capture_none) + ((value >> 8) & 3) != gpt_capture_none) { s->capt_num = 0; + } s->capture = (value >> 8) & 3; s->scpwm = (value >> 7) & 1; s->ce = (value >> 6) & 1; @@ -399,39 +412,41 @@ static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value) if (!s->inout && s->capture != gpt_capture_none) fprintf(stderr, "%s: GP timer pin must be an input " "for this capture mode\n", __func__); - if (s->trigger == gpt_trigger_none) + if (s->trigger == gpt_trigger_none) { omap_gp_timer_out(s, s->scpwm); + } /* TODO: make sure this doesn't overflow 32-bits */ s->ticks_per_sec = NANOSECONDS_PER_SECOND << (s->pre ? s->ptv + 1 : 0); omap_gp_timer_update(s); break; - case 0x28: /* TCRR */ + case 0x28: /* TCRR */ s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); s->val = value; omap_gp_timer_update(s); break; - case 0x2c: /* TLDR */ + case 0x2c: /* TLDR */ s->load_val = value; break; - case 0x30: /* TTGR */ + case 0x30: /* TTGR */ s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); s->val = s->load_val; omap_gp_timer_update(s); break; - case 0x38: /* TMAR */ + case 0x38: /* TMAR */ omap_gp_timer_sync(s); s->match_val = value; omap_gp_timer_update(s); break; - case 0x40: /* TSICR */ + case 0x40: /* TSICR */ s->posted = (value >> 2) & 1; - if (value & 2) /* How much exactly are we supposed to reset? */ + if (value & 2) { /* How much exactly are we supposed to reset? */ omap_gp_timer_reset(s); + } break; default: @@ -443,10 +458,11 @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value) { struct omap_gp_timer_s *s = opaque; - if (addr & 2) + if (addr & 2) { omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); - else + } else { s->writeh = (uint16_t) value; + } } static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr, diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c index d93a9344ed..645170c015 100644 --- a/hw/timer/omap_synctimer.c +++ b/hw/timer/omap_synctimer.c @@ -27,7 +27,8 @@ struct omap_synctimer_s { }; /* 32-kHz Sync Timer of the OMAP2 */ -static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { +static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) +{ return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 0x8000, NANOSECONDS_PER_SECOND); } @@ -42,10 +43,10 @@ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr) struct omap_synctimer_s *s = opaque; switch (addr) { - case 0x00: /* 32KSYNCNT_REV */ + case 0x00: /* 32KSYNCNT_REV */ return 0x21; - case 0x10: /* CR */ + case 0x10: /* CR */ return omap_synctimer_read(s) - s->val; } diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c index 6479ab1a8b..040668631e 100644 --- a/hw/timer/pxa2xx_timer.c +++ b/hw/timer/pxa2xx_timer.c @@ -20,42 +20,42 @@ #include "qom/object.h" #include "sysemu/watchdog.h" -#define OSMR0 0x00 -#define OSMR1 0x04 -#define OSMR2 0x08 -#define OSMR3 0x0c -#define OSMR4 0x80 -#define OSMR5 0x84 -#define OSMR6 0x88 -#define OSMR7 0x8c -#define OSMR8 0x90 -#define OSMR9 0x94 -#define OSMR10 0x98 -#define OSMR11 0x9c -#define OSCR 0x10 /* OS Timer Count */ -#define OSCR4 0x40 -#define OSCR5 0x44 -#define OSCR6 0x48 -#define OSCR7 0x4c -#define OSCR8 0x50 -#define OSCR9 0x54 -#define OSCR10 0x58 -#define OSCR11 0x5c -#define OSSR 0x14 /* Timer status register */ -#define OWER 0x18 -#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ -#define OMCR4 0xc0 /* OS Match Control registers */ -#define OMCR5 0xc4 -#define OMCR6 0xc8 -#define OMCR7 0xcc -#define OMCR8 0xd0 -#define OMCR9 0xd4 -#define OMCR10 0xd8 -#define OMCR11 0xdc -#define OSNR 0x20 - -#define PXA25X_FREQ 3686400 /* 3.6864 MHz */ -#define PXA27X_FREQ 3250000 /* 3.25 MHz */ +#define OSMR0 0x00 +#define OSMR1 0x04 +#define OSMR2 0x08 +#define OSMR3 0x0c +#define OSMR4 0x80 +#define OSMR5 0x84 +#define OSMR6 0x88 +#define OSMR7 0x8c +#define OSMR8 0x90 +#define OSMR9 0x94 +#define OSMR10 0x98 +#define OSMR11 0x9c +#define OSCR 0x10 /* OS Timer Count */ +#define OSCR4 0x40 +#define OSCR5 0x44 +#define OSCR6 0x48 +#define OSCR7 0x4c +#define OSCR8 0x50 +#define OSCR9 0x54 +#define OSCR10 0x58 +#define OSCR11 0x5c +#define OSSR 0x14 /* Timer status register */ +#define OWER 0x18 +#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ +#define OMCR4 0xc0 /* OS Match Control registers */ +#define OMCR5 0xc4 +#define OMCR6 0xc8 +#define OMCR7 0xcc +#define OMCR8 0xd0 +#define OMCR9 0xd4 +#define OMCR10 0xd8 +#define OMCR11 0xdc +#define OSNR 0x20 + +#define PXA25X_FREQ 3686400 /* 3.6864 MHz */ +#define PXA27X_FREQ 3250000 /* 3.25 MHz */ static int pxa2xx_timer4_freq[8] = { [0] = 0, @@ -108,7 +108,7 @@ struct PXA2xxTimerInfo { PXA2xxTimer4 tm4[8]; }; -#define PXA2XX_TIMER_HAVE_TM4 0 +#define PXA2XX_TIMER_HAVE_TM4 0 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s) { @@ -125,7 +125,7 @@ static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) now_vm = s->clock + muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND); - for (i = 0; i < 4; i ++) { + for (i = 0; i < 4; i++) { new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), NANOSECONDS_PER_SECOND, s->freq); timer_mod(s->timer[i].qtimer, new_qemu); @@ -141,10 +141,11 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) int counter; assert(n < ARRAY_SIZE(counters)); - if (s->tm4[n].control & (1 << 7)) + if (s->tm4[n].control & (1 << 7)) { counter = n; - else + } else { counter = counters[n]; + } if (!s->tm4[counter].freq) { timer_del(s->tm4[n].tm.qtimer); @@ -167,52 +168,71 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, int tm = 0; switch (offset) { - case OSMR3: tm ++; + case OSMR3: + tm++; /* fall through */ - case OSMR2: tm ++; + case OSMR2: + tm++; /* fall through */ - case OSMR1: tm ++; + case OSMR1: + tm++; /* fall through */ case OSMR0: return s->timer[tm].value; - case OSMR11: tm ++; + case OSMR11: + tm++; /* fall through */ - case OSMR10: tm ++; + case OSMR10: + tm++; /* fall through */ - case OSMR9: tm ++; + case OSMR9: + tm++; /* fall through */ - case OSMR8: tm ++; + case OSMR8: + tm++; /* fall through */ - case OSMR7: tm ++; + case OSMR7: + tm++; /* fall through */ - case OSMR6: tm ++; + case OSMR6: + tm++; /* fall through */ - case OSMR5: tm ++; + case OSMR5: + tm++; /* fall through */ case OSMR4: - if (!pxa2xx_timer_has_tm4(s)) + if (!pxa2xx_timer_has_tm4(s)) { goto badreg; + } return s->tm4[tm].tm.value; case OSCR: return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->lastload, s->freq, NANOSECONDS_PER_SECOND); - case OSCR11: tm ++; + case OSCR11: + tm++; /* fall through */ - case OSCR10: tm ++; + case OSCR10: + tm++; /* fall through */ - case OSCR9: tm ++; + case OSCR9: + tm++; /* fall through */ - case OSCR8: tm ++; + case OSCR8: + tm++; /* fall through */ - case OSCR7: tm ++; + case OSCR7: + tm++; /* fall through */ - case OSCR6: tm ++; + case OSCR6: + tm++; /* fall through */ - case OSCR5: tm ++; + case OSCR5: + tm++; /* fall through */ case OSCR4: - if (!pxa2xx_timer_has_tm4(s)) + if (!pxa2xx_timer_has_tm4(s)) { goto badreg; + } if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { if (s->tm4[tm - 1].freq) @@ -224,35 +244,44 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, s->snapshot = s->tm4[tm - 1].clock; } - if (!s->tm4[tm].freq) + if (!s->tm4[tm].freq) { return s->tm4[tm].clock; + } return s->tm4[tm].clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->tm4[tm].lastload, s->tm4[tm].freq, NANOSECONDS_PER_SECOND); case OIER: return s->irq_enabled; - case OSSR: /* Status register */ + case OSSR: /* Status register */ return s->events; case OWER: return s->reset3; - case OMCR11: tm ++; + case OMCR11: + tm++; /* fall through */ - case OMCR10: tm ++; + case OMCR10: + tm++; /* fall through */ - case OMCR9: tm ++; + case OMCR9: + tm++; /* fall through */ - case OMCR8: tm ++; + case OMCR8: + tm++; /* fall through */ - case OMCR7: tm ++; + case OMCR7: + tm++; /* fall through */ - case OMCR6: tm ++; + case OMCR6: + tm++; /* fall through */ - case OMCR5: tm ++; + case OMCR5: + tm++; /* fall through */ case OMCR4: - if (!pxa2xx_timer_has_tm4(s)) + if (!pxa2xx_timer_has_tm4(s)) { goto badreg; + } return s->tm4[tm].control; case OSNR: return s->snapshot; @@ -277,33 +306,44 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; switch (offset) { - case OSMR3: tm ++; + case OSMR3: + tm++; /* fall through */ - case OSMR2: tm ++; + case OSMR2: + tm++; /* fall through */ - case OSMR1: tm ++; + case OSMR1: + tm++; /* fall through */ case OSMR0: s->timer[tm].value = value; pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; - case OSMR11: tm ++; + case OSMR11: + tm++; /* fall through */ - case OSMR10: tm ++; + case OSMR10: + tm++; /* fall through */ - case OSMR9: tm ++; + case OSMR9: + tm++; /* fall through */ - case OSMR8: tm ++; + case OSMR8: + tm++; /* fall through */ - case OSMR7: tm ++; + case OSMR7: + tm++; /* fall through */ - case OSMR6: tm ++; + case OSMR6: + tm++; /* fall through */ - case OSMR5: tm ++; + case OSMR5: + tm++; /* fall through */ case OSMR4: - if (!pxa2xx_timer_has_tm4(s)) + if (!pxa2xx_timer_has_tm4(s)) { goto badreg; + } s->tm4[tm].tm.value = value; pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); break; @@ -313,23 +353,31 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, s->clock = value; pxa2xx_timer_update(s, s->lastload); break; - case OSCR11: tm ++; + case OSCR11: + tm++; /* fall through */ - case OSCR10: tm ++; + case OSCR10: + tm++; /* fall through */ - case OSCR9: tm ++; + case OSCR9: + tm++; /* fall through */ - case OSCR8: tm ++; + case OSCR8: + tm++; /* fall through */ - case OSCR7: tm ++; + case OSCR7: + tm++; /* fall through */ - case OSCR6: tm ++; + case OSCR6: + tm++; /* fall through */ - case OSCR5: tm ++; + case OSCR5: + tm++; /* fall through */ case OSCR4: - if (!pxa2xx_timer_has_tm4(s)) + if (!pxa2xx_timer_has_tm4(s)) { goto badreg; + } s->tm4[tm].oldclock = s->tm4[tm].clock; s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); s->tm4[tm].clock = value; @@ -338,27 +386,33 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, case OIER: s->irq_enabled = value & 0xfff; break; - case OSSR: /* Status register */ + case OSSR: /* Status register */ value &= s->events; s->events &= ~value; - for (i = 0; i < 4; i ++, value >>= 1) - if (value & 1) + for (i = 0; i < 4; i++, value >>= 1) + if (value & 1) { qemu_irq_lower(s->timer[i].irq); - if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value) + } + if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value) { qemu_irq_lower(s->irq4); + } break; - case OWER: /* XXX: Reset on OSMR3 match? */ + case OWER: /* XXX: Reset on OSMR3 match? */ s->reset3 = value; break; - case OMCR7: tm ++; + case OMCR7: + tm++; /* fall through */ - case OMCR6: tm ++; + case OMCR6: + tm++; /* fall through */ - case OMCR5: tm ++; + case OMCR5: + tm++; /* fall through */ case OMCR4: - if (!pxa2xx_timer_has_tm4(s)) + if (!pxa2xx_timer_has_tm4(s)) { goto badreg; + } s->tm4[tm].control = value & 0x0ff; /* XXX Stop if running (shouldn't happen) */ if ((value & (1 << 7)) || tm == 0) @@ -368,15 +422,20 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); } break; - case OMCR11: tm ++; + case OMCR11: + tm++; /* fall through */ - case OMCR10: tm ++; + case OMCR10: + tm++; /* fall through */ - case OMCR9: tm ++; + case OMCR9: + tm++; /* fall through */ - case OMCR8: tm += 4; - if (!pxa2xx_timer_has_tm4(s)) + case OMCR8: + tm += 4; + if (!pxa2xx_timer_has_tm4(s)) { goto badreg; + } s->tm4[tm].control = value & 0x3ff; /* XXX Stop if running (shouldn't happen) */ if ((value & (1 << 7)) || !(tm & 1)) @@ -428,12 +487,15 @@ static void pxa2xx_timer_tick4(void *opaque) PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info; pxa2xx_timer_tick(&t->tm); - if (t->control & (1 << 3)) + if (t->control & (1 << 3)) { t->clock = 0; - if (t->control & (1 << 6)) + } + if (t->control & (1 << 6)) { pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4); - if (i->events & 0xff0) + } + if (i->events & 0xff0) { qemu_irq_raise(i->irq4); + } } static int pxa25x_timer_post_load(void *opaque, int version_id) @@ -446,8 +508,9 @@ static int pxa25x_timer_post_load(void *opaque, int version_id) pxa2xx_timer_update(s, now); if (pxa2xx_timer_has_tm4(s)) - for (i = 0; i < 8; i ++) + for (i = 0; i < 8; i++) { pxa2xx_timer_update4(s, now, i); + } return 0; } @@ -474,7 +537,7 @@ static void pxa2xx_timer_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; - for (i = 0; i < 4; i ++) { + for (i = 0; i < 4; i++) { s->timer[i].value = 0; sysbus_init_irq(sbd, &s->timer[i].irq); s->timer[i].info = s; @@ -486,7 +549,7 @@ static void pxa2xx_timer_realize(DeviceState *dev, Error **errp) if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) { sysbus_init_irq(sbd, &s->irq4); - for (i = 0; i < 8; i ++) { + for (i = 0; i < 8; i++) { s->tm4[i].tm.value = 0; s->tm4[i].tm.info = s; s->tm4[i].tm.num = i + 4; diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index 4c6caee113..9c6d434a4b 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -16,57 +16,57 @@ #include "qom/object.h" /* Interrupt numbers */ -# define PXA2XX_PIC_SSP3 0 -# define PXA2XX_PIC_USBH2 2 -# define PXA2XX_PIC_USBH1 3 -# define PXA2XX_PIC_KEYPAD 4 -# define PXA2XX_PIC_PWRI2C 6 -# define PXA25X_PIC_HWUART 7 -# define PXA27X_PIC_OST_4_11 7 -# define PXA2XX_PIC_GPIO_0 8 -# define PXA2XX_PIC_GPIO_1 9 -# define PXA2XX_PIC_GPIO_X 10 -# define PXA2XX_PIC_I2S 13 -# define PXA26X_PIC_ASSP 15 -# define PXA25X_PIC_NSSP 16 -# define PXA27X_PIC_SSP2 16 -# define PXA2XX_PIC_LCD 17 -# define PXA2XX_PIC_I2C 18 -# define PXA2XX_PIC_ICP 19 -# define PXA2XX_PIC_STUART 20 -# define PXA2XX_PIC_BTUART 21 -# define PXA2XX_PIC_FFUART 22 -# define PXA2XX_PIC_MMC 23 -# define PXA2XX_PIC_SSP 24 -# define PXA2XX_PIC_DMA 25 -# define PXA2XX_PIC_OST_0 26 -# define PXA2XX_PIC_RTC1HZ 30 -# define PXA2XX_PIC_RTCALARM 31 +# define PXA2XX_PIC_SSP3 0 +# define PXA2XX_PIC_USBH2 2 +# define PXA2XX_PIC_USBH1 3 +# define PXA2XX_PIC_KEYPAD 4 +# define PXA2XX_PIC_PWRI2C 6 +# define PXA25X_PIC_HWUART 7 +# define PXA27X_PIC_OST_4_11 7 +# define PXA2XX_PIC_GPIO_0 8 +# define PXA2XX_PIC_GPIO_1 9 +# define PXA2XX_PIC_GPIO_X 10 +# define PXA2XX_PIC_I2S 13 +# define PXA26X_PIC_ASSP 15 +# define PXA25X_PIC_NSSP 16 +# define PXA27X_PIC_SSP2 16 +# define PXA2XX_PIC_LCD 17 +# define PXA2XX_PIC_I2C 18 +# define PXA2XX_PIC_ICP 19 +# define PXA2XX_PIC_STUART 20 +# define PXA2XX_PIC_BTUART 21 +# define PXA2XX_PIC_FFUART 22 +# define PXA2XX_PIC_MMC 23 +# define PXA2XX_PIC_SSP 24 +# define PXA2XX_PIC_DMA 25 +# define PXA2XX_PIC_OST_0 26 +# define PXA2XX_PIC_RTC1HZ 30 +# define PXA2XX_PIC_RTCALARM 31 /* DMA requests */ -# define PXA2XX_RX_RQ_I2S 2 -# define PXA2XX_TX_RQ_I2S 3 -# define PXA2XX_RX_RQ_BTUART 4 -# define PXA2XX_TX_RQ_BTUART 5 -# define PXA2XX_RX_RQ_FFUART 6 -# define PXA2XX_TX_RQ_FFUART 7 -# define PXA2XX_RX_RQ_SSP1 13 -# define PXA2XX_TX_RQ_SSP1 14 -# define PXA2XX_RX_RQ_SSP2 15 -# define PXA2XX_TX_RQ_SSP2 16 -# define PXA2XX_RX_RQ_ICP 17 -# define PXA2XX_TX_RQ_ICP 18 -# define PXA2XX_RX_RQ_STUART 19 -# define PXA2XX_TX_RQ_STUART 20 -# define PXA2XX_RX_RQ_MMCI 21 -# define PXA2XX_TX_RQ_MMCI 22 -# define PXA2XX_USB_RQ(x) ((x) + 24) -# define PXA2XX_RX_RQ_SSP3 66 -# define PXA2XX_TX_RQ_SSP3 67 - -# define PXA2XX_SDRAM_BASE 0xa0000000 -# define PXA2XX_INTERNAL_BASE 0x5c000000 -# define PXA2XX_INTERNAL_SIZE 0x40000 +# define PXA2XX_RX_RQ_I2S 2 +# define PXA2XX_TX_RQ_I2S 3 +# define PXA2XX_RX_RQ_BTUART 4 +# define PXA2XX_TX_RQ_BTUART 5 +# define PXA2XX_RX_RQ_FFUART 6 +# define PXA2XX_TX_RQ_FFUART 7 +# define PXA2XX_RX_RQ_SSP1 13 +# define PXA2XX_TX_RQ_SSP1 14 +# define PXA2XX_RX_RQ_SSP2 15 +# define PXA2XX_TX_RQ_SSP2 16 +# define PXA2XX_RX_RQ_ICP 17 +# define PXA2XX_TX_RQ_ICP 18 +# define PXA2XX_RX_RQ_STUART 19 +# define PXA2XX_TX_RQ_STUART 20 +# define PXA2XX_RX_RQ_MMCI 21 +# define PXA2XX_TX_RQ_MMCI 22 +# define PXA2XX_USB_RQ(x) ((x) + 24) +# define PXA2XX_RX_RQ_SSP3 66 +# define PXA2XX_TX_RQ_SSP3 67 + +# define PXA2XX_SDRAM_BASE 0xa0000000 +# define PXA2XX_INTERNAL_BASE 0x5c000000 +# define PXA2XX_INTERNAL_SIZE 0x40000 /* pxa2xx_pic.c */ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu); @@ -189,7 +189,7 @@ struct PXA2xxI2SState { uint32_t fifo[16]; }; -# define PA_FMT "0x%08lx" +# define PA_FMT "0x%08lx" PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision); PXA2xxState *pxa255_init(unsigned int sdram_size); diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h index e986b28c52..7e5e7ca60b 100644 --- a/include/hw/arm/sharpsl.h +++ b/include/hw/arm/sharpsl.h @@ -11,7 +11,7 @@ /* zaurus.c */ -#define SL_PXA_PARAM_BASE 0xa0000a00 +#define SL_PXA_PARAM_BASE 0xa0000a00 void sl_bootparam_write(hwaddr ptr); #endif diff --git a/include/hw/arm/soc_dma.h b/include/hw/arm/soc_dma.h index e93a7499a8..bcdb91425a 100644 --- a/include/hw/arm/soc_dma.h +++ b/include/hw/arm/soc_dma.h @@ -54,7 +54,7 @@ struct soc_dma_ch_s { int bytes; /* Initialised by the DMA module, call soc_dma_ch_update after writing. */ enum soc_dma_access_type type[2]; - hwaddr vaddr[2]; /* Updated by .transfer_fn(). */ + hwaddr vaddr[2]; /* Updated by .transfer_fn(). */ /* Private */ void *paddr[2]; soc_dma_io_t io_fn[2]; @@ -70,7 +70,7 @@ struct soc_dma_ch_s { struct soc_dma_s { /* Following fields are set by the SoC DMA module and can be used * by anybody. */ - uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ + uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ qemu_irq *drq; void *opaque; int64_t freq; diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index a43875cb09..9a07372fd9 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -86,8 +86,8 @@ extern bool use_neon_instructions; #endif /* used for function call generation */ -#define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_STACK_ALIGN 8 +#define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN