From patchwork Wed Dec 11 00:57:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 299658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D09592C02A6 for ; Wed, 11 Dec 2013 11:58:03 +1100 (EST) Received: from localhost ([::1]:51996 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqY7m-0000vs-6Y for incoming@patchwork.ozlabs.org; Tue, 10 Dec 2013 19:58:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47454) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqY7R-0000vd-Vp for qemu-devel@nongnu.org; Tue, 10 Dec 2013 19:57:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqY7N-0006RR-IV for qemu-devel@nongnu.org; Tue, 10 Dec 2013 19:57:41 -0500 Received: from mail-wg0-f48.google.com ([74.125.82.48]:51365) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqY7N-0006RM-Aa for qemu-devel@nongnu.org; Tue, 10 Dec 2013 19:57:37 -0500 Received: by mail-wg0-f48.google.com with SMTP id z12so5780439wgg.27 for ; Tue, 10 Dec 2013 16:57:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:sender:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=6xmGtPfDoX0n8lz6IOgoGcDcKzH3MMKJI6KixrpPlrA=; b=dPS7OoXxHBbjl09eaki2Utp59up7/IkW/hts491585qd7mqMJ3KcP8aGBkojKNEqvM /3FynZQo57HjsykjpmiL13dfzzkBKmtEIu+1MEoWg7W3u4EqJjwXjGlCKs+PCBEHIibM j+aVgJ5jwtU5o/Cx/JI2XHLk+bgphTJVgtG770nqx5cSptQmTNgSuvvylmHBNUQ8FY2m VqfdEjkTQ7X4bDSrlu0NphUEpqXu6dub1iC55/ibEYwGJ6JFSIkblDTePPztfpBqLgKV ac1DecA4q+P9GPntpt60umO3//8fB7/FP43N9GfT8r+rhzsCrGgKQR0rQ2AWSaa2qpP6 3+fg== X-Gm-Message-State: ALoCoQlrHg0t3nvSP3U8KHA2Uh5brJIJbiP7m1gsAlm60xjvsJkNXiq0Ry7BV7BHv1g0Qr2uwSwR MIME-Version: 1.0 X-Received: by 10.194.241.228 with SMTP id wl4mr24064927wjc.2.1386723456197; Tue, 10 Dec 2013 16:57:36 -0800 (PST) Received: by 10.227.13.9 with HTTP; Tue, 10 Dec 2013 16:57:36 -0800 (PST) In-Reply-To: References: <2d8e428867da815b6164b59bc46eaf28d6f76590.1386053678.git.peter.crosthwaite@xilinx.com> Date: Wed, 11 Dec 2013 10:57:36 +1000 X-Google-Sender-Auth: Onntq6r4rIOA3vQXbN6WiIidODM Message-ID: From: Peter Crosthwaite To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.82.48 Cc: QEMU Developers , Mark Langsdorf , =?ISO-8859-1?Q?Andreas_F=E4rber?= Subject: Re: [Qemu-devel] [PATCH arm-devs v3 3/9] target-arm: Define and use ARM_FEATURE_CBAR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Sat, Dec 7, 2013 at 12:12 AM, Peter Maydell wrote: > On 3 December 2013 07:00, Peter Crosthwaite > wrote: >> Some processors (notably A9 within Highbank) define and use the >> CP15 configuration base address (CBAR). This is vendor specific >> so its best implemented as a CPU property (otherwise we would need >> vendor specific child classes for every ARM implementation). >> >> This patch prepares support for converting CBAR reset value to >> a CPU property by moving the CP registration out of the CPU >> init fn, as registration will need to happen at realize time >> to pick up any property updates. The easiest way to do this >> is via definition of a new ARM_FEATURE to flag the existence >> of the register. >> >> Signed-off-by: Peter Crosthwaite >> --- >> changed since v2: >> msg typo: existence >> Enable CBAR for a15 as well >> >> target-arm/cpu.c | 12 +++--------- >> target-arm/cpu.h | 1 + >> target-arm/helper.c | 9 +++++++++ >> 3 files changed, 13 insertions(+), 9 deletions(-) >> >> diff --git a/target-arm/cpu.c b/target-arm/cpu.c >> index d40f2a7..90413ee 100644 >> --- a/target-arm/cpu.c >> +++ b/target-arm/cpu.c >> @@ -590,6 +590,7 @@ static void cortex_a9_initfn(Object *obj) >> * and valid configurations; we don't model A9UP). >> */ >> set_feature(&cpu->env, ARM_FEATURE_V7MP); >> + set_feature(&cpu->env, ARM_FEATURE_CBAR); >> cpu->midr = 0x410fc090; >> cpu->reset_fpsid = 0x41033090; >> cpu->mvfr0 = 0x11110222; >> @@ -612,15 +613,7 @@ static void cortex_a9_initfn(Object *obj) >> cpu->clidr = (1 << 27) | (1 << 24) | 3; >> cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ >> cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ >> - { >> - ARMCPRegInfo cbar = { >> - .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, >> - .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, >> - .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) >> - }; >> - define_one_arm_cp_reg(cpu, &cbar); >> - define_arm_cp_regs(cpu, cortexa9_cp_reginfo); >> - } >> + define_arm_cp_regs(cpu, cortexa9_cp_reginfo); >> } >> >> #ifndef CONFIG_USER_ONLY >> @@ -657,6 +650,7 @@ static void cortex_a15_initfn(Object *obj) >> set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); >> set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); >> set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); >> + set_feature(&cpu->env, ARM_FEATURE_CBAR); >> set_feature(&cpu->env, ARM_FEATURE_LPAE); >> cpu->midr = 0x412fc0f1; >> cpu->reset_fpsid = 0x410430f0; >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index 9f110f1..859750a 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -461,6 +461,7 @@ enum arm_features { >> ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ >> ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ >> ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ >> + ARM_FEATURE_CBAR, /* has cp15 CBAR */ >> ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ >> ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ >> ARM_FEATURE_V8, > > env->features gets migrated, so reordering feature bits breaks > cross-version migration; better just to add at the end of the list. > Done: Peter > Otherwise > Reviewed-by: Peter Maydell > > thanks > -- PMM > diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 318642e..947a1e7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -463,11 +463,11 @@ enum arm_features { ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ - ARM_FEATURE_CBAR, /* has cp15 CBAR */ ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ ARM_FEATURE_V8, ARM_FEATURE_AARCH64, /* supports 64 bit mode */ + ARM_FEATURE_CBAR, /* has cp15 CBAR */ }; Regards,