From patchwork Thu Apr 5 00:32:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 150873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 01542B6EF1 for ; Thu, 5 Apr 2012 16:14:43 +1000 (EST) Received: from localhost ([::1]:54206 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SFacY-0005hP-9P for incoming@patchwork.ozlabs.org; Wed, 04 Apr 2012 20:32:14 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48730) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SFacR-0005gy-Ot for qemu-devel@nongnu.org; Wed, 04 Apr 2012 20:32:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SFacP-0002SB-Tw for qemu-devel@nongnu.org; Wed, 04 Apr 2012 20:32:07 -0400 Received: from mail-bk0-f45.google.com ([209.85.214.45]:49734) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SFacP-0002OW-Mn for qemu-devel@nongnu.org; Wed, 04 Apr 2012 20:32:05 -0400 Received: by bkcjg9 with SMTP id jg9so982472bkc.4 for ; Wed, 04 Apr 2012 17:32:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding:x-gm-message-state; bh=vSOsuJKU8c+cx/SnDdiF6XZAHCNgRoAgPSqZpIfvezk=; b=TbrcSBKPh3a9OgHLKMsLRGKqaqD9QgJ74RqoXqTYBIKyx9hIVwXHFPkyQBGPWCidAd V4lKKomU9eGp4GHWeT/tkP1KU3b3yXjXlI4Frh/69+0fSKLOEQkyuTDgpmhOn4FwRp6w 4Jd9zcZP/XoRsFrks+bPlgJlOrcgowjEARfiLS940+iOYWoR+geXf29Q67Y9I+H/vr4H Np8nLX+pYkYN0CeJzBMN799hp7JEk5PJg0V5cM1L/Jxc69Epg+ebg3Xbr34q/4mqwiK9 HahKqTl4rlsgJrd56iZbynLEIY5/fhyD6lJZ1ejHW//Cni+2ZMQ/H98NM4f3XvZ10EaX efEw== MIME-Version: 1.0 Received: by 10.204.153.215 with SMTP id l23mr229620bkw.11.1333585920323; Wed, 04 Apr 2012 17:32:00 -0700 (PDT) Received: by 10.204.52.201 with HTTP; Wed, 4 Apr 2012 17:32:00 -0700 (PDT) In-Reply-To: <201204041752.56850.paul@codesourcery.com> References: <201204032222.21836.paul@codesourcery.com> <201204041752.56850.paul@codesourcery.com> Date: Thu, 5 Apr 2012 10:32:00 +1000 Message-ID: From: Peter Crosthwaite To: Paul Brook X-Gm-Message-State: ALoCoQkhODDn5ckYPyGjqqqd4oaoP7OHPl8VZZ14jLCjfMFAI8Ug97S0iVkPYzUPtY+jft1oouO7 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.214.45 Cc: Peter Maydell , qemu-devel@nongnu.org, john.williams@petalogix.com, edgar.iglesias@gmail.com Subject: Re: [Qemu-devel] [RFC PATCH v1 1/4] SPI: initial support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org >> >> It may be a case though that ssi is a superclass of spi - all SPI >> devices are SSI devices but not all SSI devices are SPI? To that end >> can we make SPI a child object of SSI with the desired extra behaviors >> mentioned in this thread? This kind of stuff is the whole reason for >> QOM. > > I don't believe there is any difference between SSI and SPI.  It's the exact > same thing - the same way that many devices support a "two-wire interface" > that is actually just I2C with a different name. > > The behavior of the CS pin varies between devices.  It sounds like you need a > bit of extra logic not present in the current ssi code.  You should fix that, > not invent a whole new bus. Ok then in that case we are extending SSI to have these as optional API features. Before withing any implementation, can I get some consensus on the following approach: 1: extend SSISlave to have the set_cs fuction: > Paul Peter --- a/hw/ssi.h +++ b/hw/ssi.h @@ -29,6 +29,7 @@ typedef struct SSISlaveClass { int (*init)(SSISlave *dev); uint32_t (*transfer)(SSISlave *dev, uint32_t val); + int (*set_cs)(SSISlave *dev, int state); } SSISlaveClass; struct SSISlave { 2: set up SSI bus as a multi-slave bus: --- a/hw/ssi.h +++ b/hw/ssi.h @@ -38,12 +38,13 @@ struct SSISlave { #define SSI_SLAVE_FROM_QDEV(dev) DO_UPCAST(SSISlave, qdev, dev) #define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) -DeviceState *ssi_create_slave(SSIBus *bus, const char *name); +DeviceState *ssi_create_slave(SSIBus *bus, const char *name, int slave); /* Master interface. */ -SSIBus *ssi_create_bus(DeviceState *parent, const char *name); +SSIBus *ssi_create_bus(DeviceState *parent, const char *name, int num_slaves); uint32_t ssi_transfer(SSIBus *bus, uint32_t val); +uint32_t ssi_select_slave(SSIBus *bus, int slave); /* max111x.c */ 3: add support for flagging sdi/sdo bits as tristated: --- a/hw/ssi.h +++ b/hw/ssi.h @@ -28,7 +28,11 @@ typedef struct SSISlaveClass { DeviceClass parent_class; int (*init)(SSISlave *dev); - uint32_t (*transfer)(SSISlave *dev, uint32_t val); + /* transfer data. If z if provided, *z is the tristate mask + * It is initially populated with tristate value for tx, and + * on return should be populated with tristate for rx + */ + uint32_t (*transfer)(SSISlave *dev, uint32_t val, uint32_t *z); } SSISlaveClass; >