From patchwork Tue Apr 17 12:28:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Starikovskiy X-Patchwork-Id: 153154 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 27A55B707E for ; Tue, 17 Apr 2012 22:28:55 +1000 (EST) Received: from localhost ([::1]:57687 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SK7We-0006PY-TP for incoming@patchwork.ozlabs.org; Tue, 17 Apr 2012 08:28:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:41862) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SK7WS-0006PD-KI for qemu-devel@nongnu.org; Tue, 17 Apr 2012 08:28:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SK7WQ-0006ss-Rk for qemu-devel@nongnu.org; Tue, 17 Apr 2012 08:28:40 -0400 Received: from mail-we0-f173.google.com ([74.125.82.173]:32920) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SK7WQ-0006si-IH for qemu-devel@nongnu.org; Tue, 17 Apr 2012 08:28:38 -0400 Received: by werp12 with SMTP id p12so4629917wer.4 for ; Tue, 17 Apr 2012 05:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=0ABxJ906aAcCI9Ri0kZ2X+IVoAn59uisRa0CG4MwHHA=; b=PLWC3CoT7ih03OZzrncrwRsyv3KehlcAA0Ot07r9VdyzYcE1WNVVAjwqNQdv4tj3Es D4qII9qqHTMO+gx6vlmvbsDunB+0H2Gmm7C48LWtDLIdXebSV8k4ClO2eT7q8nKL0Q8q W/MkyJ6AUFMd2pHF1m39y+uD0kyCxy/AUevACvdd9NFl60M6XAhSbmO6o9ifeN9NmPwS 1SbuKM3Bp5N8P70N0rZKpzRFBQV0QzPWbWltVl7L8e2cwzwBCZJGgz1nyxKPFMpHaEWd alm1rH3yt/QJk8cbGUKnFZ7EQVaii6qKBNynk1CylS7sJ1rhE/KX5nZiZ9mNt3wGKPti G6YA== MIME-Version: 1.0 Received: by 10.180.106.9 with SMTP id gq9mr28019629wib.17.1334665716446; Tue, 17 Apr 2012 05:28:36 -0700 (PDT) Received: by 10.180.8.136 with HTTP; Tue, 17 Apr 2012 05:28:36 -0700 (PDT) In-Reply-To: References: <4F8D5664.7000304@gmail.com> <4F8D5BFE.40204@gmail.com> Date: Tue, 17 Apr 2012 16:28:36 +0400 Message-ID: From: Alexey Starikovskiy To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 74.125.82.173 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v2] Undefine SWP instruction unless SCTLR.SW bit is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ARM v7MP deprecates use of SWP instruction and only defines it if OS explicitly requests it via setting SCTLR.SW bit. Such a request is expected to occur only once during OS init, thus only static checking for this bit and flush of all translations is done on SCTLR change. Signed-off-by: Alexey Starikovskiy --- target-arm/helper.c | 2 ++ target-arm/translate.c | 9 +++++++++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 28f127b..e8b17a4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1491,6 +1491,8 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(env, 1); + /* This may enable/disable SWP instruction, so do TB flush too */ + tb_flush(env); break; case 1: /* Auxiliary control register. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { diff --git a/target-arm/translate.c b/target-arm/translate.c index 7a3c7d6..452b300 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7415,6 +7415,15 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) } tcg_temp_free(addr); } else { +#ifndef CONFIG_USER_ONLY + if (arm_feature(env, ARM_FEATURE_V7MP) && + !(env->cp15.c1_sys & (1 << 10))) { + /* Check if SCTLR.SW is set. Any change to SCTLR + * invalidates all translations, so we are safe. + */ + goto illegal_op; + } +#endif /* SWP instruction */ rm = (insn) & 0xf;