From patchwork Sat Sep 24 18:22:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 116245 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AE62BB6F70 for ; Sun, 25 Sep 2011 04:57:13 +1000 (EST) Received: from localhost ([::1]:51307 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7Wt1-00063F-RY for incoming@patchwork.ozlabs.org; Sat, 24 Sep 2011 14:23:39 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7Wsl-0005T7-GS for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:23:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R7Wsg-0003lo-F4 for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:23:23 -0400 Received: from mail-qy0-f173.google.com ([209.85.216.173]:47497) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7Wsg-0003KH-Bz for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:23:18 -0400 Received: by mail-qy0-f173.google.com with SMTP id 1so7609784qyc.4 for ; Sat, 24 Sep 2011 11:23:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; bh=fgBE4h/LyVQJBfYa8BLri6kZ6829gLsasYzPaSnzIuk=; b=q5bgDJKtBFyzBN76A9k4Kez7JTCgr+S5BWBXbCOHHqWZMuzMPp0KQvIxD098V9tRB5 3rV7cZM87NGjVrrxygOCzqhHxWQHHNt0qiS18oxxJZkI/bZiS0lk/VJa23sJZoJIxhvj R/JMTczubcHtF6DuEaiKJAXCbsrOD0tspa7NU= Received: by 10.224.216.68 with SMTP id hh4mr2607598qab.309.1316888598128; Sat, 24 Sep 2011 11:23:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.6.129 with HTTP; Sat, 24 Sep 2011 11:22:58 -0700 (PDT) From: Blue Swirl Date: Sat, 24 Sep 2011 18:22:58 +0000 Message-ID: To: qemu-devel X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.216.173 Subject: [Qemu-devel] [PATCH 20/26] Sparc: convert int_helper to trace framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Blue Swirl --- target-sparc/int_helper.c | 41 +++++++++++++++-------------------------- trace-events | 7 +++++++ 2 files changed, 22 insertions(+), 26 deletions(-) uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64 + +# target-sparc/int_helper.c +int_helper_set_softint(uint32_t softint) "new %08x" +int_helper_clear_softint(uint32_t softint) "new %08x" +int_helper_write_softint(uint32_t softint) "new %08x" +int_helper_icache_freeze(void) "Instruction cache: freeze" +int_helper_dcache_freeze(void) "Data cache: freeze" diff --git a/target-sparc/int_helper.c b/target-sparc/int_helper.c index 3361eed..76a3fdb 100644 --- a/target-sparc/int_helper.c +++ b/target-sparc/int_helper.c @@ -19,24 +19,9 @@ #include "cpu.h" #include "helper.h" +#include "trace.h" //#define DEBUG_PCALL -//#define DEBUG_PSTATE -//#define DEBUG_CACHE_CONTROL - -#ifdef DEBUG_PSTATE -#define DPRINTF_PSTATE(fmt, ...) \ - do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF_PSTATE(fmt, ...) do {} while (0) -#endif - -#ifdef DEBUG_CACHE_CONTROL -#define DPRINTF_CACHE_CONTROL(fmt, ...) \ - do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) -#endif #ifdef TARGET_SPARC64 #ifdef DEBUG_PCALL @@ -286,35 +271,39 @@ trap_state *cpu_tsptr(CPUState* env) return &env->ts[env->tl & MAXTL_MASK]; } -static void do_modify_softint(CPUState *env, const char *operation, - uint32_t value) +static bool do_modify_softint(CPUState *env, uint32_t value) { if (env->softint != value) { env->softint = value; - DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint); #if !defined(CONFIG_USER_ONLY) if (cpu_interrupts_enabled(env)) { cpu_check_irqs(env); } #endif + return true; } + return false; } void helper_set_softint(CPUState *env, uint64_t value) { - do_modify_softint(env, "helper_set_softint", - env->softint | (uint32_t)value); + if (do_modify_softint(env, env->softint | (uint32_t)value)) { + trace_int_helper_set_softint(env->softint); + } } void helper_clear_softint(CPUState *env, uint64_t value) { - do_modify_softint(env, "helper_clear_softint", - env->softint & (uint32_t)~value); + if (do_modify_softint(env, env->softint & (uint32_t)~value)) { + trace_int_helper_clear_softint(env->softint); + } } void helper_write_softint(CPUState *env, uint64_t value) { - do_modify_softint(env, "helper_write_softint", (uint32_t)value); + if (do_modify_softint(env, (uint32_t)value)) { + trace_int_helper_write_softint(env->softint); + } } #else #if !defined(CONFIG_USER_ONLY) @@ -327,7 +316,7 @@ static void leon3_cache_control_int(CPUState *env) state = env->cache_control & CACHE_STATE_MASK; if (state == CACHE_ENABLED) { state = CACHE_FROZEN; - DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n"); + trace_int_helper_icache_freeze(); } env->cache_control &= ~CACHE_STATE_MASK; @@ -339,7 +328,7 @@ static void leon3_cache_control_int(CPUState *env) state = (env->cache_control >> 2) & CACHE_STATE_MASK; if (state == CACHE_ENABLED) { state = CACHE_FROZEN; - DPRINTF_CACHE_CONTROL("Data cache: freeze\n"); + trace_int_helper_dcache_freeze(); } env->cache_control &= ~(CACHE_STATE_MASK << 2); diff --git a/trace-events b/trace-events index 718e0d5..1058bc0 100644 --- a/trace-events +++ b/trace-events @@ -512,3 +512,10 @@ mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at %"PRIx64" context mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx,