From patchwork Sat Sep 24 18:19:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 116241 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A479D1007D3 for ; Sun, 25 Sep 2011 04:20:06 +1000 (EST) Received: from localhost ([::1]:46596 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7WpL-0006wA-OT for incoming@patchwork.ozlabs.org; Sat, 24 Sep 2011 14:19:51 -0400 Received: from eggs.gnu.org ([140.186.70.92]:49899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7Wp9-0006pY-EB for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:19:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R7Wow-0002zy-R3 for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:19:39 -0400 Received: from mail-qy0-f180.google.com ([209.85.216.180]:56939) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7Wow-0002zu-Hk for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:19:26 -0400 Received: by qyc1 with SMTP id 1so4722235qyc.4 for ; Sat, 24 Sep 2011 11:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; bh=F9bt9uiKvHgR9+mm4fnhHBERjtFlZDuhi6DR0RXFRXg=; b=OOF6HZpJoZ/NPDf8DoUutFLZ50zF8FgHo+s3L0WrSk/OEpXk3FLp9Z783sAcncxmrY lYIkBc1RhBqhEPnt/xwQzhPWLoy6153hqTQQgJtyp2M5WJ9Ivb4J1/E0bfOJ118G1+V1 Ic3Xw/m/G7dpZ9hF1E1fM+6zS0zg6AFzfSa5E= Received: by 10.224.216.68 with SMTP id hh4mr2606048qab.309.1316888366078; Sat, 24 Sep 2011 11:19:26 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.6.129 with HTTP; Sat, 24 Sep 2011 11:19:06 -0700 (PDT) From: Blue Swirl Date: Sat, 24 Sep 2011 18:19:06 +0000 Message-ID: To: qemu-devel X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.216.180 Subject: [Qemu-devel] [PATCH 10/26] Sparc: avoid AREG0 for float and VIS ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make floating point and VIS ops take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl --- Makefile.target | 2 +- target-sparc/fop_helper.c | 70 ++++++------ target-sparc/helper.h | 172 ++++++++++++++-------------- target-sparc/translate.c | 270 +++++++++++++++++++++++---------------------- target-sparc/vis_helper.c | 41 ++++--- 5 files changed, 281 insertions(+), 274 deletions(-) @@ -57,7 +58,7 @@ target_ulong helper_alignaddr(target_ulong addr, target_ulong offset) return tmp & ~7ULL; } -void helper_faligndata(void) +void helper_faligndata(CPUState *env) { uint64_t tmp; @@ -101,7 +102,7 @@ typedef union { float32 f; } VIS32; -void helper_fpmerge(void) +void helper_fpmerge(CPUState *env) { VIS64 s, d; @@ -121,7 +122,7 @@ void helper_fpmerge(void) DT0 = d.d; } -void helper_fmul8x16(void) +void helper_fmul8x16(CPUState *env) { VIS64 s, d; uint32_t tmp; @@ -145,7 +146,7 @@ void helper_fmul8x16(void) DT0 = d.d; } -void helper_fmul8x16al(void) +void helper_fmul8x16al(CPUState *env) { VIS64 s, d; uint32_t tmp; @@ -169,7 +170,7 @@ void helper_fmul8x16al(void) DT0 = d.d; } -void helper_fmul8x16au(void) +void helper_fmul8x16au(CPUState *env) { VIS64 s, d; uint32_t tmp; @@ -193,7 +194,7 @@ void helper_fmul8x16au(void) DT0 = d.d; } -void helper_fmul8sux16(void) +void helper_fmul8sux16(CPUState *env) { VIS64 s, d; uint32_t tmp; @@ -217,7 +218,7 @@ void helper_fmul8sux16(void) DT0 = d.d; } -void helper_fmul8ulx16(void) +void helper_fmul8ulx16(CPUState *env) { VIS64 s, d; uint32_t tmp; @@ -241,7 +242,7 @@ void helper_fmul8ulx16(void) DT0 = d.d; } -void helper_fmuld8sux16(void) +void helper_fmuld8sux16(CPUState *env) { VIS64 s, d; uint32_t tmp; @@ -264,7 +265,7 @@ void helper_fmuld8sux16(void) DT0 = d.d; } -void helper_fmuld8ulx16(void) +void helper_fmuld8ulx16(CPUState *env) { VIS64 s, d; uint32_t tmp; @@ -287,7 +288,7 @@ void helper_fmuld8ulx16(void) DT0 = d.d; } -void helper_fexpand(void) +void helper_fexpand(CPUState *env) { VIS32 s; VIS64 d; @@ -303,7 +304,7 @@ void helper_fexpand(void) } #define VIS_HELPER(name, F) \ - void name##16(void) \ + void name##16(CPUState *env) \ { \ VIS64 s, d; \ \ @@ -318,7 +319,8 @@ void helper_fexpand(void) DT0 = d.d; \ } \ \ - uint32_t name##16s(uint32_t src1, uint32_t src2) \ + uint32_t name##16s(CPUState *env, uint32_t src1, \ + uint32_t src2) \ { \ VIS32 s, d; \ \ @@ -331,7 +333,7 @@ void helper_fexpand(void) return d.l; \ } \ \ - void name##32(void) \ + void name##32(CPUState *env) \ { \ VIS64 s, d; \ \ @@ -344,7 +346,8 @@ void helper_fexpand(void) DT0 = d.d; \ } \ \ - uint32_t name##32s(uint32_t src1, uint32_t src2) \ + uint32_t name##32s(CPUState *env, uint32_t src1, \ + uint32_t src2) \ { \ VIS32 s, d; \ \ @@ -362,7 +365,7 @@ VIS_HELPER(helper_fpadd, FADD) VIS_HELPER(helper_fpsub, FSUB) #define VIS_CMPHELPER(name, F) \ - uint64_t name##16(void) \ + uint64_t name##16(CPUState *env) \ { \ VIS64 s, d; \ \ @@ -378,7 +381,7 @@ VIS_HELPER(helper_fpsub, FSUB) return d.ll; \ } \ \ - uint64_t name##32(void) \ + uint64_t name##32(CPUState *env) \ { \ VIS64 s, d; \ \ diff --git a/Makefile.target b/Makefile.target index 278e722..9f70978 100644 --- a/Makefile.target +++ b/Makefile.target @@ -95,7 +95,7 @@ tcg/tcg.o: cpu.h # HELPER_CFLAGS is used for all the code compiled with static register # variables -op_helper.o fop_helper.o vis_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS) +op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS) # Note: this is a workaround. The real fix is to avoid compiling # cpu_signal_handler() in user-exec.c. diff --git a/target-sparc/fop_helper.c b/target-sparc/fop_helper.c index ddd0af9..23502f3 100644 --- a/target-sparc/fop_helper.c +++ b/target-sparc/fop_helper.c @@ -18,7 +18,6 @@ */ #include "cpu.h" -#include "dyngen-exec.h" #include "helper.h" #define DT0 (env->dt0) @@ -26,10 +25,11 @@ #define QT0 (env->qt0) #define QT1 (env->qt1) -#define F_HELPER(name, p) void helper_f##name##p(void) +#define F_HELPER(name, p) void helper_f##name##p(CPUState *env) #define F_BINOP(name) \ - float32 helper_f ## name ## s (float32 src1, float32 src2) \ + float32 helper_f ## name ## s (CPUState * env, float32 src1,\ + float32 src2) \ { \ return float32_ ## name (src1, src2, &env->fp_status); \ } \ @@ -48,14 +48,14 @@ F_BINOP(mul); F_BINOP(div); #undef F_BINOP -void helper_fsmuld(float32 src1, float32 src2) +void helper_fsmuld(CPUState *env, float32 src1, float32 src2) { DT0 = float64_mul(float32_to_float64(src1, &env->fp_status), float32_to_float64(src2, &env->fp_status), &env->fp_status); } -void helper_fdmulq(void) +void helper_fdmulq(CPUState *env) { QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status), float64_to_float128(DT1, &env->fp_status), @@ -80,23 +80,23 @@ F_HELPER(neg, q) #endif /* Integer to float conversion. */ -float32 helper_fitos(int32_t src) +float32 helper_fitos(CPUState *env, int32_t src) { return int32_to_float32(src, &env->fp_status); } -void helper_fitod(int32_t src) +void helper_fitod(CPUState *env, int32_t src) { DT0 = int32_to_float64(src, &env->fp_status); } -void helper_fitoq(int32_t src) +void helper_fitoq(CPUState *env, int32_t src) { QT0 = int32_to_float128(src, &env->fp_status); } #ifdef TARGET_SPARC64 -float32 helper_fxtos(void) +float32 helper_fxtos(CPUState *env) { return int64_to_float32(*((int64_t *)&DT1), &env->fp_status); } @@ -114,64 +114,64 @@ F_HELPER(xto, q) #undef F_HELPER /* floating point conversion */ -float32 helper_fdtos(void) +float32 helper_fdtos(CPUState *env) { return float64_to_float32(DT1, &env->fp_status); } -void helper_fstod(float32 src) +void helper_fstod(CPUState *env, float32 src) { DT0 = float32_to_float64(src, &env->fp_status); } -float32 helper_fqtos(void) +float32 helper_fqtos(CPUState *env) { return float128_to_float32(QT1, &env->fp_status); } -void helper_fstoq(float32 src) +void helper_fstoq(CPUState *env, float32 src) { QT0 = float32_to_float128(src, &env->fp_status); } -void helper_fqtod(void) +void helper_fqtod(CPUState *env) { DT0 = float128_to_float64(QT1, &env->fp_status); } -void helper_fdtoq(void) +void helper_fdtoq(CPUState *env) { QT0 = float64_to_float128(DT1, &env->fp_status); } /* Float to integer conversion. */ -int32_t helper_fstoi(float32 src) +int32_t helper_fstoi(CPUState *env, float32 src) { return float32_to_int32_round_to_zero(src, &env->fp_status); } -int32_t helper_fdtoi(void) +int32_t helper_fdtoi(CPUState *env) { return float64_to_int32_round_to_zero(DT1, &env->fp_status); } -int32_t helper_fqtoi(void) +int32_t helper_fqtoi(CPUState *env) { return float128_to_int32_round_to_zero(QT1, &env->fp_status); } #ifdef TARGET_SPARC64 -void helper_fstox(float32 src) +void helper_fstox(CPUState *env, float32 src) { *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status); } -void helper_fdtox(void) +void helper_fdtox(CPUState *env) { *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status); } -void helper_fqtox(void) +void helper_fqtox(CPUState *env) { *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status); } @@ -183,34 +183,34 @@ float32 helper_fabss(float32 src) } #ifdef TARGET_SPARC64 -void helper_fabsd(void) +void helper_fabsd(CPUState *env) { DT0 = float64_abs(DT1); } -void helper_fabsq(void) +void helper_fabsq(CPUState *env) { QT0 = float128_abs(QT1); } #endif -float32 helper_fsqrts(float32 src) +float32 helper_fsqrts(CPUState *env, float32 src) { return float32_sqrt(src, &env->fp_status); } -void helper_fsqrtd(void) +void helper_fsqrtd(CPUState *env) { DT0 = float64_sqrt(DT1, &env->fp_status); } -void helper_fsqrtq(void) +void helper_fsqrtq(CPUState *env) { QT0 = float128_sqrt(QT1, &env->fp_status); } #define GEN_FCMP(name, size, reg1, reg2, FS, E) \ - void glue(helper_, name) (void) \ + void glue(helper_, name) (CPUState *env) \ { \ env->fsr &= FSR_FTT_NMASK; \ if (E && (glue(size, _is_any_nan)(reg1) || \ @@ -246,7 +246,7 @@ void helper_fsqrtq(void) } \ } #define GEN_FCMPS(name, size, FS, E) \ - void glue(helper_, name)(float32 src1, float32 src2) \ + void glue(helper_, name)(CPUState *env, float32 src1, float32 src2) \ { \ env->fsr &= FSR_FTT_NMASK; \ if (E && (glue(size, _is_any_nan)(src1) || \ @@ -318,7 +318,7 @@ GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); #endif #undef GEN_FCMPS -void helper_check_ieee_exceptions(void) +void helper_check_ieee_exceptions(CPUState *env) { target_ulong status; @@ -352,12 +352,12 @@ void helper_check_ieee_exceptions(void) } } -void helper_clear_float_exceptions(void) +void helper_clear_float_exceptions(CPUState *env) { set_float_exception_flags(0, &env->fp_status); } -static inline void set_fsr(void) +static inline void set_fsr(CPUState *env) { int rnd_mode; @@ -379,16 +379,16 @@ static inline void set_fsr(void) set_float_rounding_mode(rnd_mode, &env->fp_status); } -void helper_ldfsr(uint32_t new_fsr) +void helper_ldfsr(CPUState *env, uint32_t new_fsr) { env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK); - set_fsr(); + set_fsr(env); } #ifdef TARGET_SPARC64 -void helper_ldxfsr(uint64_t new_fsr) +void helper_ldxfsr(CPUState *env, uint64_t new_fsr) { env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK); - set_fsr(); + set_fsr(env); } #endif diff --git a/target-sparc/helper.h b/target-sparc/helper.h index a452666..fe63846 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -16,8 +16,8 @@ DEF_HELPER_0(rdccr, tl) DEF_HELPER_1(wrccr, void, tl) DEF_HELPER_0(rdcwp, tl) DEF_HELPER_1(wrcwp, void, tl) -DEF_HELPER_2(array8, tl, tl, tl) -DEF_HELPER_2(alignaddr, tl, tl, tl) +DEF_HELPER_3(array8, tl, env, tl, tl) +DEF_HELPER_3(alignaddr, tl, env, tl, tl) DEF_HELPER_1(popc, tl, tl) DEF_HELPER_3(ldda_asi, void, tl, int, int) DEF_HELPER_4(ldf_asi, void, tl, int, int, int) @@ -47,116 +47,116 @@ DEF_HELPER_2(stqf, void, tl, int) DEF_HELPER_4(ld_asi, i64, tl, int, int, int) DEF_HELPER_4(st_asi, void, tl, i64, int, int) #endif -DEF_HELPER_1(ldfsr, void, i32) -DEF_HELPER_0(check_ieee_exceptions, void) -DEF_HELPER_0(clear_float_exceptions, void) +DEF_HELPER_2(ldfsr, void, env, i32) +DEF_HELPER_1(check_ieee_exceptions, void, env) +DEF_HELPER_1(clear_float_exceptions, void, env) DEF_HELPER_1(fabss, f32, f32) -DEF_HELPER_1(fsqrts, f32, f32) -DEF_HELPER_0(fsqrtd, void) -DEF_HELPER_2(fcmps, void, f32, f32) -DEF_HELPER_0(fcmpd, void) -DEF_HELPER_2(fcmpes, void, f32, f32) -DEF_HELPER_0(fcmped, void) -DEF_HELPER_0(fsqrtq, void) -DEF_HELPER_0(fcmpq, void) -DEF_HELPER_0(fcmpeq, void) +DEF_HELPER_2(fsqrts, f32, env, f32) +DEF_HELPER_1(fsqrtd, void, env) +DEF_HELPER_3(fcmps, void, env, f32, f32) +DEF_HELPER_1(fcmpd, void, env) +DEF_HELPER_3(fcmpes, void, env, f32, f32) +DEF_HELPER_1(fcmped, void, env) +DEF_HELPER_1(fsqrtq, void, env) +DEF_HELPER_1(fcmpq, void, env) +DEF_HELPER_1(fcmpeq, void, env) #ifdef TARGET_SPARC64 -DEF_HELPER_1(ldxfsr, void, i64) -DEF_HELPER_0(fabsd, void) -DEF_HELPER_2(fcmps_fcc1, void, f32, f32) -DEF_HELPER_2(fcmps_fcc2, void, f32, f32) -DEF_HELPER_2(fcmps_fcc3, void, f32, f32) -DEF_HELPER_0(fcmpd_fcc1, void) -DEF_HELPER_0(fcmpd_fcc2, void) -DEF_HELPER_0(fcmpd_fcc3, void) -DEF_HELPER_2(fcmpes_fcc1, void, f32, f32) -DEF_HELPER_2(fcmpes_fcc2, void, f32, f32) -DEF_HELPER_2(fcmpes_fcc3, void, f32, f32) -DEF_HELPER_0(fcmped_fcc1, void) -DEF_HELPER_0(fcmped_fcc2, void) -DEF_HELPER_0(fcmped_fcc3, void) -DEF_HELPER_0(fabsq, void) -DEF_HELPER_0(fcmpq_fcc1, void) -DEF_HELPER_0(fcmpq_fcc2, void) -DEF_HELPER_0(fcmpq_fcc3, void) -DEF_HELPER_0(fcmpeq_fcc1, void) -DEF_HELPER_0(fcmpeq_fcc2, void) -DEF_HELPER_0(fcmpeq_fcc3, void) +DEF_HELPER_2(ldxfsr, void, env, i64) +DEF_HELPER_1(fabsd, void, env) +DEF_HELPER_3(fcmps_fcc1, void, env, f32, f32) +DEF_HELPER_3(fcmps_fcc2, void, env, f32, f32) +DEF_HELPER_3(fcmps_fcc3, void, env, f32, f32) +DEF_HELPER_1(fcmpd_fcc1, void, env) +DEF_HELPER_1(fcmpd_fcc2, void, env) +DEF_HELPER_1(fcmpd_fcc3, void, env) +DEF_HELPER_3(fcmpes_fcc1, void, env, f32, f32) +DEF_HELPER_3(fcmpes_fcc2, void, env, f32, f32) +DEF_HELPER_3(fcmpes_fcc3, void, env, f32, f32) +DEF_HELPER_1(fcmped_fcc1, void, env) +DEF_HELPER_1(fcmped_fcc2, void, env) +DEF_HELPER_1(fcmped_fcc3, void, env) +DEF_HELPER_1(fabsq, void, env) +DEF_HELPER_1(fcmpq_fcc1, void, env) +DEF_HELPER_1(fcmpq_fcc2, void, env) +DEF_HELPER_1(fcmpq_fcc3, void, env) +DEF_HELPER_1(fcmpeq_fcc1, void, env) +DEF_HELPER_1(fcmpeq_fcc2, void, env) +DEF_HELPER_1(fcmpeq_fcc3, void, env) #endif DEF_HELPER_2(raise_exception, void, env, int) DEF_HELPER_0(shutdown, void) -#define F_HELPER_0_0(name) DEF_HELPER_0(f ## name, void) -#define F_HELPER_DQ_0_0(name) \ - F_HELPER_0_0(name ## d); \ - F_HELPER_0_0(name ## q) +#define F_HELPER_0_1(name) DEF_HELPER_1(f ## name, void, env) +#define F_HELPER_DQ_0_1(name) \ + F_HELPER_0_1(name ## d); \ + F_HELPER_0_1(name ## q) -F_HELPER_DQ_0_0(add); -F_HELPER_DQ_0_0(sub); -F_HELPER_DQ_0_0(mul); -F_HELPER_DQ_0_0(div); +F_HELPER_DQ_0_1(add); +F_HELPER_DQ_0_1(sub); +F_HELPER_DQ_0_1(mul); +F_HELPER_DQ_0_1(div); -DEF_HELPER_2(fadds, f32, f32, f32) -DEF_HELPER_2(fsubs, f32, f32, f32) -DEF_HELPER_2(fmuls, f32, f32, f32) -DEF_HELPER_2(fdivs, f32, f32, f32) +DEF_HELPER_3(fadds, f32, env, f32, f32) +DEF_HELPER_3(fsubs, f32, env, f32, f32) +DEF_HELPER_3(fmuls, f32, env, f32, f32) +DEF_HELPER_3(fdivs, f32, env, f32, f32) -DEF_HELPER_2(fsmuld, void, f32, f32) -F_HELPER_0_0(dmulq); +DEF_HELPER_3(fsmuld, void, env, f32, f32) +F_HELPER_0_1(dmulq); DEF_HELPER_1(fnegs, f32, f32) -DEF_HELPER_1(fitod, void, s32) -DEF_HELPER_1(fitoq, void, s32) +DEF_HELPER_2(fitod, void, env, s32) +DEF_HELPER_2(fitoq, void, env, s32) -DEF_HELPER_1(fitos, f32, s32) +DEF_HELPER_2(fitos, f32, env, s32) #ifdef TARGET_SPARC64 -DEF_HELPER_0(fnegd, void) -DEF_HELPER_0(fnegq, void) -DEF_HELPER_0(fxtos, i32) -F_HELPER_DQ_0_0(xto); +DEF_HELPER_1(fnegd, void, env) +DEF_HELPER_1(fnegq, void, env) +DEF_HELPER_1(fxtos, i32, env) +F_HELPER_DQ_0_1(xto); #endif -DEF_HELPER_0(fdtos, f32) -DEF_HELPER_1(fstod, void, f32) -DEF_HELPER_0(fqtos, f32) -DEF_HELPER_1(fstoq, void, f32) -F_HELPER_0_0(qtod); -F_HELPER_0_0(dtoq); -DEF_HELPER_1(fstoi, s32, f32) -DEF_HELPER_0(fdtoi, s32) -DEF_HELPER_0(fqtoi, s32) +DEF_HELPER_1(fdtos, f32, env) +DEF_HELPER_2(fstod, void, env, f32) +DEF_HELPER_1(fqtos, f32, env) +DEF_HELPER_2(fstoq, void, env, f32) +F_HELPER_0_1(qtod); +F_HELPER_0_1(dtoq); +DEF_HELPER_2(fstoi, s32, env, f32) +DEF_HELPER_1(fdtoi, s32, env) +DEF_HELPER_1(fqtoi, s32, env) #ifdef TARGET_SPARC64 -DEF_HELPER_1(fstox, void, i32) -F_HELPER_0_0(dtox); -F_HELPER_0_0(qtox); -F_HELPER_0_0(aligndata); +DEF_HELPER_2(fstox, void, env, i32) +F_HELPER_0_1(dtox); +F_HELPER_0_1(qtox); +F_HELPER_0_1(aligndata); -F_HELPER_0_0(pmerge); -F_HELPER_0_0(mul8x16); -F_HELPER_0_0(mul8x16al); -F_HELPER_0_0(mul8x16au); -F_HELPER_0_0(mul8sux16); -F_HELPER_0_0(mul8ulx16); -F_HELPER_0_0(muld8sux16); -F_HELPER_0_0(muld8ulx16); -F_HELPER_0_0(expand); +F_HELPER_0_1(pmerge); +F_HELPER_0_1(mul8x16); +F_HELPER_0_1(mul8x16al); +F_HELPER_0_1(mul8x16au); +F_HELPER_0_1(mul8sux16); +F_HELPER_0_1(mul8ulx16); +F_HELPER_0_1(muld8sux16); +F_HELPER_0_1(muld8ulx16); +F_HELPER_0_1(expand); #define VIS_HELPER(name) \ - F_HELPER_0_0(name##16); \ - DEF_HELPER_2(f ## name ## 16s, i32, i32, i32) \ - F_HELPER_0_0(name##32); \ - DEF_HELPER_2(f ## name ## 32s, i32, i32, i32) + F_HELPER_0_1(name##16); \ + DEF_HELPER_3(f ## name ## 16s, i32, env, i32, i32) \ + F_HELPER_0_1(name##32); \ + DEF_HELPER_3(f ## name ## 32s, i32, env, i32, i32) VIS_HELPER(padd); VIS_HELPER(psub); #define VIS_CMPHELPER(name) \ - DEF_HELPER_0(f##name##16, i64); \ - DEF_HELPER_0(f##name##32, i64) + DEF_HELPER_1(f##name##16, i64, env); \ + DEF_HELPER_1(f##name##32, i64, env) VIS_CMPHELPER(cmpgt); VIS_CMPHELPER(cmpeq); VIS_CMPHELPER(cmple); VIS_CMPHELPER(cmpne); #endif -#undef F_HELPER_0_0 -#undef F_HELPER_DQ_0_0 +#undef F_HELPER_0_1 +#undef F_HELPER_DQ_0_1 #undef VIS_HELPER #undef VIS_CMPHELPER DEF_HELPER_0(compute_psr, void); diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 9dd6b34..8c05c44 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -1405,16 +1405,16 @@ static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmps(r_rs1, r_rs2); + gen_helper_fcmps(cpu_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmps_fcc1(r_rs1, r_rs2); + gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmps_fcc2(r_rs1, r_rs2); + gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmps_fcc3(r_rs1, r_rs2); + gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2); break; } } @@ -1423,16 +1423,16 @@ static inline void gen_op_fcmpd(int fccno) { switch (fccno) { case 0: - gen_helper_fcmpd(); + gen_helper_fcmpd(cpu_env); break; case 1: - gen_helper_fcmpd_fcc1(); + gen_helper_fcmpd_fcc1(cpu_env); break; case 2: - gen_helper_fcmpd_fcc2(); + gen_helper_fcmpd_fcc2(cpu_env); break; case 3: - gen_helper_fcmpd_fcc3(); + gen_helper_fcmpd_fcc3(cpu_env); break; } } @@ -1441,16 +1441,16 @@ static inline void gen_op_fcmpq(int fccno) { switch (fccno) { case 0: - gen_helper_fcmpq(); + gen_helper_fcmpq(cpu_env); break; case 1: - gen_helper_fcmpq_fcc1(); + gen_helper_fcmpq_fcc1(cpu_env); break; case 2: - gen_helper_fcmpq_fcc2(); + gen_helper_fcmpq_fcc2(cpu_env); break; case 3: - gen_helper_fcmpq_fcc3(); + gen_helper_fcmpq_fcc3(cpu_env); break; } } @@ -1459,16 +1459,16 @@ static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpes(r_rs1, r_rs2); + gen_helper_fcmpes(cpu_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpes_fcc1(r_rs1, r_rs2); + gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpes_fcc2(r_rs1, r_rs2); + gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpes_fcc3(r_rs1, r_rs2); + gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2); break; } } @@ -1477,16 +1477,16 @@ static inline void gen_op_fcmped(int fccno) { switch (fccno) { case 0: - gen_helper_fcmped(); + gen_helper_fcmped(cpu_env); break; case 1: - gen_helper_fcmped_fcc1(); + gen_helper_fcmped_fcc1(cpu_env); break; case 2: - gen_helper_fcmped_fcc2(); + gen_helper_fcmped_fcc2(cpu_env); break; case 3: - gen_helper_fcmped_fcc3(); + gen_helper_fcmped_fcc3(cpu_env); break; } } @@ -1495,16 +1495,16 @@ static inline void gen_op_fcmpeq(int fccno) { switch (fccno) { case 0: - gen_helper_fcmpeq(); + gen_helper_fcmpeq(cpu_env); break; case 1: - gen_helper_fcmpeq_fcc1(); + gen_helper_fcmpeq_fcc1(cpu_env); break; case 2: - gen_helper_fcmpeq_fcc2(); + gen_helper_fcmpeq_fcc2(cpu_env); break; case 3: - gen_helper_fcmpeq_fcc3(); + gen_helper_fcmpeq_fcc3(cpu_env); break; } } @@ -1513,32 +1513,32 @@ static inline void gen_op_fcmpeq(int fccno) static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmps(r_rs1, r_rs2); + gen_helper_fcmps(cpu_env, r_rs1, r_rs2); } static inline void gen_op_fcmpd(int fccno) { - gen_helper_fcmpd(); + gen_helper_fcmpd(cpu_env); } static inline void gen_op_fcmpq(int fccno) { - gen_helper_fcmpq(); + gen_helper_fcmpq(cpu_env); } static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmpes(r_rs1, r_rs2); + gen_helper_fcmpes(cpu_env, r_rs1, r_rs2); } static inline void gen_op_fcmped(int fccno) { - gen_helper_fcmped(); + gen_helper_fcmped(cpu_env); } static inline void gen_op_fcmpeq(int fccno) { - gen_helper_fcmpeq(); + gen_helper_fcmpeq(cpu_env); } #endif @@ -1584,7 +1584,7 @@ static inline void gen_op_clear_ieee_excp_and_FTT(void) static inline void gen_clear_float_exceptions(void) { - gen_helper_clear_float_exceptions(); + gen_helper_clear_float_exceptions(cpu_env); } /* asi moves */ @@ -2383,8 +2383,8 @@ static void disas_sparc_insn(DisasContext * dc) case 0x29: /* fsqrts */ CHECK_FPU_FEATURE(dc, FSQRT); gen_clear_float_exceptions(); - gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fsqrts(cpu_tmp32, cpu_env, cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2392,8 +2392,8 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FSQRT); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fsqrtd(); - gen_helper_check_ieee_exceptions(); + gen_helper_fsqrtd(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2401,15 +2401,16 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fsqrtq(); - gen_helper_check_ieee_exceptions(); + gen_helper_fsqrtq(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0x41: /* fadds */ gen_clear_float_exceptions(); - gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fadds(cpu_tmp32, cpu_env, cpu_fpr[rs1], + cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2417,8 +2418,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_faddd(); - gen_helper_check_ieee_exceptions(); + gen_helper_faddd(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2427,15 +2428,16 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_faddq(); - gen_helper_check_ieee_exceptions(); + gen_helper_faddq(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0x45: /* fsubs */ gen_clear_float_exceptions(); - gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fsubs(cpu_tmp32, cpu_env, cpu_fpr[rs1], + cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2443,8 +2445,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fsubd(); - gen_helper_check_ieee_exceptions(); + gen_helper_fsubd(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2453,16 +2455,17 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fsubq(); - gen_helper_check_ieee_exceptions(); + gen_helper_fsubq(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0x49: /* fmuls */ CHECK_FPU_FEATURE(dc, FMUL); gen_clear_float_exceptions(); - gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fmuls(cpu_tmp32, cpu_env, cpu_fpr[rs1], + cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2471,8 +2474,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fmuld(); - gen_helper_check_ieee_exceptions(); + gen_helper_fmuld(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2482,15 +2485,16 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fmulq(); - gen_helper_check_ieee_exceptions(); + gen_helper_fmulq(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0x4d: /* fdivs */ gen_clear_float_exceptions(); - gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fdivs(cpu_tmp32, cpu_env, cpu_fpr[rs1], + cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2498,8 +2502,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdivd(); - gen_helper_check_ieee_exceptions(); + gen_helper_fdivd(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2508,16 +2512,16 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdivq(); - gen_helper_check_ieee_exceptions(); + gen_helper_fdivq(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0x69: /* fsmuld */ CHECK_FPU_FEATURE(dc, FSMULD); gen_clear_float_exceptions(); - gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fsmuld(cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2526,23 +2530,23 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdmulq(); - gen_helper_check_ieee_exceptions(); + gen_helper_fdmulq(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0xc4: /* fitos */ gen_clear_float_exceptions(); - gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fitos(cpu_tmp32, cpu_env, cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; case 0xc6: /* fdtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdtos(cpu_tmp32); - gen_helper_check_ieee_exceptions(); + gen_helper_fdtos(cpu_tmp32, cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2550,18 +2554,18 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtos(cpu_tmp32); - gen_helper_check_ieee_exceptions(); + gen_helper_fqtos(cpu_tmp32, cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; case 0xc8: /* fitod */ - gen_helper_fitod(cpu_fpr[rs2]); + gen_helper_fitod(cpu_env, cpu_fpr[rs2]); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0xc9: /* fstod */ - gen_helper_fstod(cpu_fpr[rs2]); + gen_helper_fstod(cpu_env, cpu_fpr[rs2]); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2569,42 +2573,42 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtod(); - gen_helper_check_ieee_exceptions(); + gen_helper_fqtod(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0xcc: /* fitoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_helper_fitoq(cpu_fpr[rs2]); + gen_helper_fitoq(cpu_env, cpu_fpr[rs2]); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0xcd: /* fstoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_helper_fstoq(cpu_fpr[rs2]); + gen_helper_fstoq(cpu_env, cpu_fpr[rs2]); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0xce: /* fdtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fdtoq(); + gen_helper_fdtoq(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0xd1: /* fstoi */ gen_clear_float_exceptions(); - gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fstoi(cpu_tmp32, cpu_env, cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; case 0xd2: /* fdtoi */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdtoi(cpu_tmp32); - gen_helper_check_ieee_exceptions(); + gen_helper_fdtoi(cpu_tmp32, cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2612,8 +2616,8 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtoi(cpu_tmp32); - gen_helper_check_ieee_exceptions(); + gen_helper_fqtoi(cpu_tmp32, cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; @@ -2637,42 +2641,42 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x6: /* V9 fnegd */ gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fnegd(); + gen_helper_fnegd(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x7: /* V9 fnegq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); - gen_helper_fnegq(); + gen_helper_fnegq(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0xa: /* V9 fabsd */ gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fabsd(); + gen_helper_fabsd(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0xb: /* V9 fabsq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); - gen_helper_fabsq(); + gen_helper_fabsq(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0x81: /* V9 fstox */ gen_clear_float_exceptions(); - gen_helper_fstox(cpu_fpr[rs2]); - gen_helper_check_ieee_exceptions(); + gen_helper_fstox(cpu_env, cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x82: /* V9 fdtox */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdtox(); - gen_helper_check_ieee_exceptions(); + gen_helper_fdtox(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2680,24 +2684,24 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtox(); - gen_helper_check_ieee_exceptions(); + gen_helper_fqtox(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x84: /* V9 fxtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fxtos(cpu_tmp32); - gen_helper_check_ieee_exceptions(); + gen_helper_fxtos(cpu_tmp32, cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); gen_update_fprs_dirty(rd); break; case 0x88: /* V9 fxtod */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fxtod(); - gen_helper_check_ieee_exceptions(); + gen_helper_fxtod(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2705,8 +2709,8 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fxtoq(); - gen_helper_check_ieee_exceptions(); + gen_helper_fxtoq(cpu_env); + gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; @@ -3828,14 +3832,14 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); + gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2); gen_movl_TN_reg(rd, cpu_dst); break; case 0x012: /* VIS I array16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); + gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2); tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); gen_movl_TN_reg(rd, cpu_dst); break; @@ -3843,7 +3847,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); + gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2); tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); gen_movl_TN_reg(rd, cpu_dst); break; @@ -3851,7 +3855,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); + gen_helper_alignaddr(cpu_dst, cpu_env, cpu_src1, cpu_src2); gen_movl_TN_reg(rd, cpu_dst); break; case 0x019: /* VIS II bmask */ @@ -3862,63 +3866,63 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmple16(cpu_dst); + gen_helper_fcmple16(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x022: /* VIS I fcmpne16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpne16(cpu_dst); + gen_helper_fcmpne16(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x024: /* VIS I fcmple32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmple32(cpu_dst); + gen_helper_fcmple32(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x026: /* VIS I fcmpne32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpne32(cpu_dst); + gen_helper_fcmpne32(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x028: /* VIS I fcmpgt16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpgt16(cpu_dst); + gen_helper_fcmpgt16(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x02a: /* VIS I fcmpeq16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpeq16(cpu_dst); + gen_helper_fcmpeq16(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x02c: /* VIS I fcmpgt32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpgt32(cpu_dst); + gen_helper_fcmpgt32(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x02e: /* VIS I fcmpeq32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpeq32(cpu_dst); + gen_helper_fcmpeq32(cpu_dst, cpu_env); gen_movl_TN_reg(rd, cpu_dst); break; case 0x031: /* VIS I fmul8x16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8x16(); + gen_helper_fmul8x16(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3926,7 +3930,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8x16au(); + gen_helper_fmul8x16au(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3934,7 +3938,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8x16al(); + gen_helper_fmul8x16al(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3942,7 +3946,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8sux16(); + gen_helper_fmul8sux16(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3950,7 +3954,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8ulx16(); + gen_helper_fmul8ulx16(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3958,7 +3962,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmuld8sux16(); + gen_helper_fmuld8sux16(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3966,7 +3970,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmuld8ulx16(); + gen_helper_fmuld8ulx16(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3980,7 +3984,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_faligndata(); + gen_helper_faligndata(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3988,7 +3992,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpmerge(); + gen_helper_fpmerge(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -3999,7 +4003,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fexpand(); + gen_helper_fexpand(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -4007,13 +4011,13 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpadd16(); + gen_helper_fpadd16(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x051: /* VIS I fpadd16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpadd16s(cpu_fpr[rd], + gen_helper_fpadd16s(cpu_env, cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); gen_update_fprs_dirty(rd); break; @@ -4021,13 +4025,13 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpadd32(); + gen_helper_fpadd32(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x053: /* VIS I fpadd32s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpadd32s(cpu_fpr[rd], + gen_helper_fpadd32s(cpu_env, cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); gen_update_fprs_dirty(rd); break; @@ -4035,13 +4039,13 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpsub16(); + gen_helper_fpsub16(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x055: /* VIS I fpsub16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpsub16s(cpu_fpr[rd], + gen_helper_fpsub16s(cpu_env, cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); gen_update_fprs_dirty(rd); break; @@ -4049,13 +4053,13 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpsub32(); + gen_helper_fpsub32(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x057: /* VIS I fpsub32s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpsub32s(cpu_fpr[rd], + gen_helper_fpsub32s(cpu_env, cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); gen_update_fprs_dirty(rd); break; @@ -4659,16 +4663,16 @@ static void disas_sparc_insn(DisasContext * dc) gen_address_mask(dc, cpu_addr); if (rd == 1) { tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); - gen_helper_ldxfsr(cpu_tmp64); + gen_helper_ldxfsr(cpu_env, cpu_tmp64); } else { tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); - gen_helper_ldfsr(cpu_tmp32); + gen_helper_ldfsr(cpu_env, cpu_tmp32); } #else { tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); - gen_helper_ldfsr(cpu_tmp32); + gen_helper_ldfsr(cpu_env, cpu_tmp32); } #endif break; diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index 87a86ef..a22c10b 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -18,7 +18,6 @@ */ #include "cpu.h" -#include "dyngen-exec.h" #include "helper.h" #define DT0 (env->dt0) @@ -34,7 +33,8 @@ #define GET_FIELD_SP(X, FROM, TO) \ GET_FIELD(X, 63 - (TO), 63 - (FROM)) -target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) +target_ulong helper_array8(CPUState *env, target_ulong pixel_addr, + target_ulong cubesize) { return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) | (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) | @@ -47,7 +47,8 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) GET_FIELD_SP(pixel_addr, 11, 12); } -target_ulong helper_alignaddr(target_ulong addr, target_ulong offset) +target_ulong helper_alignaddr(CPUState *env, target_ulong addr, + target_ulong offset) { uint64_t tmp;