@@ -2061,7 +2061,11 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
} else {
if (opc == 3) {
/* PRFM (literal) : prefetch */
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ ;
+ #else
return;
+ #endif
}
size = 2 + extract32(opc, 0, 1);
is_signed = extract32(opc, 1, 1);
@@ -2075,9 +2079,19 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
} else {
/* Only unsigned 32bit loads target 32bit registers. */
bool iss_sf = opc != 0;
-
- do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
- true, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ if (opc == 3) {
+ TCGv_i64 v = tcg_temp_new_i64();
+ do_gpr_ld(s, v, tcg_addr, size, is_signed, false,
+ true, rt, iss_sf, false);
+ tcg_temp_free_i64(v);
+ } else {
+ #endif
+ do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
+ true, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ }
+ #endif
}
tcg_temp_free_i64(tcg_addr);
}
@@ -2283,7 +2297,11 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
unallocated_encoding(s);
return;
}
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ rn = 31;
+ #else
return;
+ #endif
}
if (opc == 3 && size > 1) {
unallocated_encoding(s);
@@ -2334,9 +2352,21 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx,
iss_valid, rt, iss_sf, false);
} else {
- do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
- is_signed, is_extended, memidx,
- iss_valid, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ if (size == 3 && opc == 2) {
+ TCGv_i64 v = tcg_temp_new_i64();
+ do_gpr_ld_memidx(s, v, tcg_addr, size,
+ is_signed, is_extended, memidx,
+ iss_valid, rt, iss_sf, false);
+ tcg_temp_free_i64(v);
+ } else {
+ #endif
+ do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
+ is_signed, is_extended, memidx,
+ iss_valid, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ }
+ #endif
}
}
@@ -2383,6 +2413,9 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
bool is_signed = false;
bool is_store = false;
bool is_extended = false;
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ TCGv_i64 v = tcg_temp_new_i64();
+ #endif
TCGv_i64 tcg_rm;
TCGv_i64 tcg_addr;
@@ -2405,7 +2438,11 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
} else {
if (size == 3 && opc == 2) {
/* PRFM - prefetch */
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ rn = 31;
+ #else
return;
+ #endif
}
if (opc == 3 && size > 1) {
unallocated_encoding(s);
@@ -2422,9 +2459,17 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
tcg_addr = read_cpu_reg_sp(s, rn, 1);
tcg_rm = read_cpu_reg(s, rm, 1);
- ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
-
- tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ if ((!is_vector) &&(size == 3 && opc == 2)) {
+ ext_and_shift_reg(v, tcg_rm, opt, shift ? size : 0);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, v);
+ } else {
+ #endif
+ ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ }
+ #endif
if (is_vector) {
if (is_store) {
@@ -2439,11 +2484,25 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
do_gpr_st(s, tcg_rt, tcg_addr, size,
true, rt, iss_sf, false);
} else {
- do_gpr_ld(s, tcg_rt, tcg_addr, size,
- is_signed, is_extended,
- true, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ if (size == 3 && opc == 2) {
+ is_signed = false;
+ do_gpr_ld(s, v, tcg_addr, size,
+ is_signed, is_extended,
+ true, rt, iss_sf, false);
+ } else {
+ #endif
+ do_gpr_ld(s, tcg_rt, tcg_addr, size,
+ is_signed, is_extended,
+ true, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ }
+ #endif
}
}
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ tcg_temp_free_i64(v);
+ #endif
}
/*
@@ -2492,7 +2551,11 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
} else {
if (size == 3 && opc == 2) {
/* PRFM - prefetch */
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ rn = 31;
+ #else
return;
+ #endif
}
if (opc == 3 && size > 1) {
unallocated_encoding(s);
@@ -2523,8 +2586,20 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
do_gpr_st(s, tcg_rt, tcg_addr, size,
true, rt, iss_sf, false);
} else {
- do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended,
- true, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ if (size == 3 && opc == 2) {
+ TCGv_i64 v = tcg_temp_new_i64();
+ is_signed = false;
+ do_gpr_ld(s, v, tcg_addr, size, is_signed, is_extended,
+ true, rt, iss_sf, false);
+ tcg_temp_free_i64(v);
+ } else {
+ #endif
+ do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended,
+ true, rt, iss_sf, false);
+ #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
+ }
+ #endif
}
}
}
@@ -135,6 +135,8 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
#define DISAS_SMC 9
#define DISAS_YIELD 10
+#undef TCG_AARCH64_PREFETCH_TRANSLATE
+
#ifdef TARGET_AARCH64
void a64_translate_init(void);
void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);