From patchwork Thu Mar 5 20:25:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 446910 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1AFB714009B for ; Fri, 6 Mar 2015 07:47:57 +1100 (AEDT) Received: from localhost ([::1]:54855 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YTcgV-00056K-Ag for incoming@patchwork.ozlabs.org; Thu, 05 Mar 2015 15:47:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YTcDa-00024P-Ah for qemu-devel@nongnu.org; Thu, 05 Mar 2015 15:18:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YTcDV-0002Fw-8V for qemu-devel@nongnu.org; Thu, 05 Mar 2015 15:18:02 -0500 Received: from blu004-omc1s28.hotmail.com ([65.55.116.39]:61711) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YTcDV-0002Fa-4R for qemu-devel@nongnu.org; Thu, 05 Mar 2015 15:17:57 -0500 Received: from BLU436-SMTP174 ([65.55.116.9]) by BLU004-OMC1S28.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.22751); Thu, 5 Mar 2015 12:17:56 -0800 X-TMN: [2rBdQuTliWJ7jptza+cPpzCrsT5z0wK7] X-Originating-Email: [xili_gchen_5257@hotmail.com] Message-ID: Date: Fri, 6 Mar 2015 04:25:47 +0800 From: Chen Gang User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.10; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , Chris Metcalf , "rth@twiddle.net" , Peter Maydell , Riku Voipio , "walt@tilera.com" References: <54F8BA72.3040009@hotmail.com> In-Reply-To: X-OriginalArrivalTime: 05 Mar 2015 20:17:55.0375 (UTC) FILETIME=[771113F0:01D05781] X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 65.55.116.39 X-Mailman-Approved-At: Thu, 05 Mar 2015 15:43:10 -0500 Cc: qemu-devel Subject: [Qemu-devel] [PATCH 1/6 v5] target-tilegx: Firstly add TILE-Gx with minimized features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org It is the configure and build system support for TILE-Gx (tilegx will be used in configure and real sub-directory name), and at present, it is linux-user only. Signed-off-by: Chen Gang --- configure | 3 + default-configs/tilegx-linux-user.mak | 1 + target-tilegx/Makefile.objs | 1 + target-tilegx/cpu-qom.h | 71 ++++++++++++++++ target-tilegx/cpu.c | 153 ++++++++++++++++++++++++++++++++++ target-tilegx/cpu.h | 85 +++++++++++++++++++ target-tilegx/helper.h | 0 target-tilegx/translate.c | 53 ++++++++++++ 8 files changed, 367 insertions(+) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 target-tilegx/Makefile.objs create mode 100644 target-tilegx/cpu-qom.h create mode 100644 target-tilegx/cpu.c create mode 100644 target-tilegx/cpu.h create mode 100644 target-tilegx/helper.h create mode 100644 target-tilegx/translate.c diff --git a/configure b/configure index 7ba4bcb..9586502 100755 --- a/configure +++ b/configure @@ -5191,6 +5191,9 @@ case "$target_name" in s390x) gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml" ;; + tilegx) + TARGET_ARCH=tilegx + ;; unicore32) ;; xtensa|xtensaeb) diff --git a/default-configs/tilegx-linux-user.mak b/default-configs/tilegx-linux-user.mak new file mode 100644 index 0000000..3e47493 --- /dev/null +++ b/default-configs/tilegx-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for tilegx-linux-user diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs new file mode 100644 index 0000000..dcf2fe4 --- /dev/null +++ b/target-tilegx/Makefile.objs @@ -0,0 +1 @@ +obj-y += cpu.o translate.o diff --git a/target-tilegx/cpu-qom.h b/target-tilegx/cpu-qom.h new file mode 100644 index 0000000..4ee11e1 --- /dev/null +++ b/target-tilegx/cpu-qom.h @@ -0,0 +1,71 @@ +/* + * QEMU TILE-Gx CPU + * + * Copyright (c) 2015 Chen Gang + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ +#ifndef QEMU_TILEGX_CPU_QOM_H +#define QEMU_TILEGX_CPU_QOM_H + +#include "qom/cpu.h" + +#define TYPE_TILEGX_CPU "tilegx-cpu" + +#define TILEGX_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU) +#define TILEGX_CPU(obj) \ + OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU) +#define TILEGX_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU) + +/** + * TileGXCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * A Tile-Gx CPU model. + */ +typedef struct TileGXCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + DeviceRealize parent_realize; + void (*parent_reset)(CPUState *cpu); +} TileGXCPUClass; + +/** + * TileGXCPU: + * @env: #CPUTLGState + * + * A Tile-GX CPU. + */ +typedef struct TileGXCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUTLGState env; +} TileGXCPU; + +static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env) +{ + return container_of(env, TileGXCPU, env); +} + +#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e)) + +#endif diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c new file mode 100644 index 0000000..cf46b8b --- /dev/null +++ b/target-tilegx/cpu.c @@ -0,0 +1,153 @@ +/* + * QEMU TILE-Gx CPU + * + * Copyright (c) 2015 Chen Gang + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "cpu.h" +#include "qemu-common.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +TileGXCPU *cpu_tilegx_init(const char *cpu_model) +{ + TileGXCPU *cpu; + + cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU)); + + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); + + return cpu; +} + +static void tilegx_cpu_set_pc(CPUState *cs, vaddr value) +{ + TileGXCPU *cpu = TILEGX_CPU(cs); + + cpu->env.pc = value; +} + +static bool tilegx_cpu_has_work(CPUState *cs) +{ + return true; +} + +static void tilegx_cpu_reset(CPUState *s) +{ + TileGXCPU *cpu = TILEGX_CPU(s); + TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu); + CPUTLGState *env = &cpu->env; + + tcc->parent_reset(s); + + memset(env, 0, sizeof(CPUTLGState)); + tlb_flush(s, 1); +} + +static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev); + + cpu_reset(cs); + qemu_init_vcpu(cs); + + tcc->parent_realize(dev, errp); +} + +static void tilegx_tcg_init(void) +{ +} + +static void tilegx_cpu_initfn(Object *obj) +{ + CPUState *cs = CPU(obj); + TileGXCPU *cpu = TILEGX_CPU(obj); + CPUTLGState *env = &cpu->env; + static bool tcg_initialized; + + cs->env_ptr = env; + cpu_exec_init(env); + + if (tcg_enabled() && !tcg_initialized) { + tcg_initialized = true; + tilegx_tcg_init(); + } +} + +static const VMStateDescription vmstate_tilegx_cpu = { + .name = "cpu", + .unmigratable = 1, +}; + +static void tilegx_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index = -1; +} + +static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, + int mmu_idx) +{ + cpu_dump_state(cs, stderr, fprintf, 0); + return 1; +} + +static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + tilegx_cpu_do_interrupt(cs); + return true; + } + return false; +} + +static void tilegx_cpu_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc); + + tcc->parent_realize = dc->realize; + dc->realize = tilegx_cpu_realizefn; + + tcc->parent_reset = cc->reset; + cc->reset = tilegx_cpu_reset; + + cc->has_work = tilegx_cpu_has_work; + cc->do_interrupt = tilegx_cpu_do_interrupt; + cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt; + cc->set_pc = tilegx_cpu_set_pc; + cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault; + dc->vmsd = &vmstate_tilegx_cpu; + cc->gdb_num_core_regs = 0; +} + +static const TypeInfo tilegx_cpu_type_info = { + .name = TYPE_TILEGX_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(TileGXCPU), + .instance_init = tilegx_cpu_initfn, + .class_size = sizeof(TileGXCPUClass), + .class_init = tilegx_cpu_class_init, +}; + +static void tilegx_cpu_register_types(void) +{ + type_register_static(&tilegx_cpu_type_info); +} + +type_init(tilegx_cpu_register_types) diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h new file mode 100644 index 0000000..87dc56b --- /dev/null +++ b/target-tilegx/cpu.h @@ -0,0 +1,85 @@ +/* + * TILE-Gx virtual CPU header + * + * Copyright (c) 2015 Chen Gang + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef CPU_TILEGX_H +#define CPU_TILEGX_H + +#include "config.h" +#include "qemu-common.h" + +#define TARGET_LONG_BITS 64 + +#define CPUArchState struct CPUTLGState + +#include "exec/cpu-defs.h" +#include "fpu/softfloat.h" + +/* TILE-Gx register alias */ +#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */ +#define TILEGX_R_NR 10 /* 10 register, for syscall number */ +#define TILEGX_R_BP 52 /* 52 register, optional frame pointer */ +#define TILEGX_R_TP 53 /* TP register, thread local storage data */ +#define TILEGX_R_SP 54 /* SP register, stack pointer */ +#define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */ + +typedef struct CPUTLGState { + uint64_t regs[56]; + uint64_t pc; + CPU_COMMON +} CPUTLGState; + +#include "cpu-qom.h" + +/* TILE-Gx memory attributes */ +#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ +#define MMAP_SHIFT TARGET_PAGE_BITS +#define TARGET_PHYS_ADDR_SPACE_BITS 42 /* TILE-Gx is 42 bit physical address */ +#define TARGET_VIRT_ADDR_SPACE_BITS 64 /* TILE-Gx has 64 bit virtual address */ +#define MMU_USER_IDX 0 /* independent from both qemu and architecture */ + +#include "exec/cpu-all.h" + +int cpu_tilegx_exec(CPUTLGState *s); +int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc); + +#define cpu_exec cpu_tilegx_exec +#define cpu_gen_code cpu_tilegx_gen_code +#define cpu_signal_handler cpu_tilegx_signal_handler + +TileGXCPU *cpu_tilegx_init(const char *cpu_model); + +static inline CPUTLGState *cpu_init(const char *cpu_model) +{ + TileGXCPU *cpu = cpu_tilegx_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + +static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc, + target_ulong *cs_base, int *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = 0; +} + +#include "exec/exec-all.h" + +#endif diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h new file mode 100644 index 0000000..e69de29 diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c new file mode 100644 index 0000000..9aa82a9 --- /dev/null +++ b/target-tilegx/translate.c @@ -0,0 +1,53 @@ +/* + * QEMU TILE-Gx CPU + * + * Copyright (c) 2015 Chen Gang + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "cpu.h" +#include "qemu/log.h" +#include "disas/disas.h" +#include "tcg-op.h" +#include "exec/cpu_ldst.h" + +static inline void gen_intermediate_code_internal(TileGXCPU *cpu, + TranslationBlock *tb, + bool search_pc) +{ + /* + * FIXME: after load elf64 tilegx binary successfully, it will quit, at + * present, and will implement the related features next. + */ + qemu_log("\nLoaded elf64 tilegx successfully\n"); + qemu_log("reached code start position: [" TARGET_FMT_lx "] %s\n\n", + tb->pc, lookup_symbol(tb->pc)); + exit(0); +} + +void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb) +{ + gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false); +} + +void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb) +{ + gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true); +} + +void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos) +{ +}