From patchwork Sun Sep 25 08:10:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 116267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 620D7B6F75 for ; Sun, 25 Sep 2011 18:11:39 +1000 (EST) Received: from localhost ([::1]:43114 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7joE-0008E7-TI for incoming@patchwork.ozlabs.org; Sun, 25 Sep 2011 04:11:34 -0400 Received: from eggs.gnu.org ([140.186.70.92]:57475) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7jo7-0008Dr-Nl for qemu-devel@nongnu.org; Sun, 25 Sep 2011 04:11:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R7jo6-0007VC-4Q for qemu-devel@nongnu.org; Sun, 25 Sep 2011 04:11:27 -0400 Received: from mga01.intel.com ([192.55.52.88]:13226) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7jo5-0007V3-Pc for qemu-devel@nongnu.org; Sun, 25 Sep 2011 04:11:26 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 25 Sep 2011 01:11:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.68,439,1312182000"; d="scan'208,223"; a="70461849" Received: from pgsmsx603.gar.corp.intel.com ([10.221.43.87]) by fmsmga002.fm.intel.com with ESMTP; 25 Sep 2011 01:11:20 -0700 Received: from shsmsx602.ccr.corp.intel.com (10.239.4.104) by pgsmsx603.gar.corp.intel.com (10.221.43.87) with Microsoft SMTP Server (TLS) id 8.2.255.0; Sun, 25 Sep 2011 16:10:50 +0800 Received: from shsmsx502.ccr.corp.intel.com ([10.239.4.96]) by SHSMSX602.ccr.corp.intel.com ([10.239.4.104]) with mapi; Sun, 25 Sep 2011 16:10:49 +0800 From: "Liu, Jinsong" To: Marcelo Tosatti , Jan Kiszka , Avi Kivity , "qemu-devel@nongnu.org" Date: Sun, 25 Sep 2011 16:10:48 +0800 Thread-Topic: Qemu co-operation with kvm tsc deadline timer Thread-Index: Acx7WqH4WwOI91e8SBSXYcDOPqf7Fg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.88 Cc: "Tian, Kevin" , "kvm@vger.kernel.org" Subject: [Qemu-devel] Qemu co-operation with kvm tsc deadline timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From 7b58c09d1bb70c7ca8aa29892b08ba4a3e7b9e92 Mon Sep 17 00:00:00 2001 From: Liu Jinsong Date: Sun, 25 Sep 2011 15:48:29 +0800 Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer KVM add emulation of lapic tsc deadline timer for guest. This patch is co-operation work at qemu side. Signed-off-by: Liu, Jinsong --- target-i386/cpu.h | 4 +++- target-i386/kvm.c | 14 ++++++++++++++ target-i386/machine.c | 1 + 3 files changed, 18 insertions(+), 1 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4a6f675..52d0da2 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -283,6 +283,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe #define MSR_MTRRcap_VCNT 8 @@ -687,6 +688,7 @@ typedef struct CPUX86State { uint64_t async_pf_en_msr; uint64_t tsc; + uint64_t tsc_deadline; uint64_t mcg_status; @@ -947,7 +949,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_list_id x86_cpu_list #define cpudef_setup x86_cpudef_setup -#define CPU_SAVE_VERSION 12 +#define CPU_SAVE_VERSION 13 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 22b1dd0..ac8aa04 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -59,6 +59,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool has_msr_star; static bool has_msr_hsave_pa; +static bool has_msr_tsc_deadline; static bool has_msr_async_pf_en; static int lm_capable_kernel; @@ -568,6 +569,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hsave_pa = true; continue; } + if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { + has_msr_tsc_deadline = true; + continue; + } } } @@ -881,6 +886,9 @@ static int kvm_put_msrs(CPUState *env, int level) if (has_msr_hsave_pa) { kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); } + if (has_msr_tsc_deadline) { + kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); @@ -1127,6 +1135,9 @@ static int kvm_get_msrs(CPUState *env) if (has_msr_hsave_pa) { msrs[n++].index = MSR_VM_HSAVE_PA; } + if (has_msr_tsc_deadline) { + msrs[n++].index = MSR_IA32_TSCDEADLINE; + } if (!env->tsc_valid) { msrs[n++].index = MSR_IA32_TSC; @@ -1195,6 +1206,9 @@ static int kvm_get_msrs(CPUState *env) case MSR_IA32_TSC: env->tsc = msrs[i].data; break; + case MSR_IA32_TSCDEADLINE: + env->tsc_deadline = msrs[i].data; + break; case MSR_VM_HSAVE_PA: env->vm_hsave = msrs[i].data; break; diff --git a/target-i386/machine.c b/target-i386/machine.c index 9aca8e0..25fa97d 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -410,6 +410,7 @@ static const VMStateDescription vmstate_cpu = { VMSTATE_UINT64_V(xcr0, CPUState, 12), VMSTATE_UINT64_V(xstate_bv, CPUState, 12), VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12), + VMSTATE_UINT64_V(tsc_deadline, CPUState, 13), VMSTATE_END_OF_LIST() /* The above list is not sorted /wrt version numbers, watch out! */ },