From patchwork Fri Sep 9 18:47:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 114120 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A7DDCB71BD for ; Sat, 10 Sep 2011 04:49:08 +1000 (EST) Received: from localhost ([::1]:47562 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R268N-0004SI-5P for incoming@patchwork.ozlabs.org; Fri, 09 Sep 2011 14:49:03 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R268G-0004S1-Vo for qemu-devel@nongnu.org; Fri, 09 Sep 2011 14:48:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R268G-0006m5-1o for qemu-devel@nongnu.org; Fri, 09 Sep 2011 14:48:56 -0400 Received: from mga09.intel.com ([134.134.136.24]:53083) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R268F-0006m1-QV for qemu-devel@nongnu.org; Fri, 09 Sep 2011 14:48:55 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 09 Sep 2011 11:48:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.67,352,1309762800"; d="scan'208";a="46875761" Received: from pgsmsx602.gar.corp.intel.com ([10.221.43.81]) by orsmga001.jf.intel.com with ESMTP; 09 Sep 2011 11:48:53 -0700 Received: from pgsmsx509.gar.corp.intel.com (172.30.13.17) by pgsmsx602.gar.corp.intel.com (10.221.43.81) with Microsoft SMTP Server (TLS) id 8.2.255.0; Sat, 10 Sep 2011 02:48:01 +0800 Received: from shsmsx602.ccr.corp.intel.com (10.239.4.104) by PGSMSX509.gar.corp.intel.com (172.30.13.17) with Microsoft SMTP Server (TLS) id 8.2.255.0; Sat, 10 Sep 2011 02:48:01 +0800 Received: from shsmsx502.ccr.corp.intel.com ([10.239.4.96]) by SHSMSX602.ccr.corp.intel.com ([10.239.4.104]) with mapi; Sat, 10 Sep 2011 02:48:00 +0800 From: "Liu, Jinsong" To: Marcelo Tosatti Date: Sat, 10 Sep 2011 02:47:58 +0800 Thread-Topic: [PATCH] KVM: emulate lapic tsc deadline timer for hvm Thread-Index: AcxvH3RGX2WJ6fJhTzi8WUGn5YZenQAAECVw Message-ID: References: <4E521EF9.7020404@redhat.com> <20110823104723.GA2898@amt.cnet> <20110909125635.GA10198@amt.cnet> <20110909183636.GA24361@amt.cnet> In-Reply-To: <20110909183636.GA24361@amt.cnet> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 Cc: Avi Kivity , "kvm@vger.kernel.org" , "qemu-devel@nongnu.org" Subject: Re: [Qemu-devel] [PATCH] KVM: emulate lapic tsc deadline timer for hvm X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org >> >> My question is, which kvm_get_msrs/kvm_put_msrs routine be used by >> live migration, the routine in target-i386/kvm.c, or in >> kvm/libkvm/libkvm-x86.c? They both have ioctl >> KVM_GET_MSR_INDEX_LIST/ KVM_GET_MSRS/ KVM_SET_MSRS, but I'm not >> clear their purpose/usage difference. > > kvm_get_msrs/kvm_put_msrs in target-i386/kvm.c. kvm/ directory is > dead. Thanks to make me clear. Add it to qemu like: ================= Thanks, Jinsong ================ diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 935d08a..62ff73c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -283,6 +283,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe #define MSR_MTRRcap_VCNT 8 @@ -687,6 +688,7 @@ typedef struct CPUX86State { uint64_t async_pf_en_msr; uint64_t tsc; + uint64_t tsc_deadline; uint64_t mcg_status; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index aa843f0..206fcad 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -59,6 +59,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool has_msr_star; static bool has_msr_hsave_pa; +static bool has_msr_tsc_deadline; static bool has_msr_async_pf_en; static int lm_capable_kernel; @@ -571,6 +572,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hsave_pa = true; continue; } + if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { + has_msr_tsc_deadline = true; + continue; + } } } @@ -899,6 +904,9 @@ static int kvm_put_msrs(CPUState *env, int level) if (has_msr_hsave_pa) { kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); } + if (has_msr_tsc_deadline) { + kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); @@ -1145,6 +1153,9 @@ static int kvm_get_msrs(CPUState *env) if (has_msr_hsave_pa) { msrs[n++].index = MSR_VM_HSAVE_PA; } + if (has_msr_tsc_deadline) { + msrs[n++].index = MSR_IA32_TSCDEADLINE; + } if (!env->tsc_valid) { msrs[n++].index = MSR_IA32_TSC; @@ -1213,6 +1224,9 @@ static int kvm_get_msrs(CPUState *env) case MSR_IA32_TSC: env->tsc = msrs[i].data; break; + case MSR_IA32_TSCDEADLINE: + env->tsc_deadline = msrs[i].data; + break; case MSR_VM_HSAVE_PA: env->vm_hsave = msrs[i].data; break;