From patchwork Tue Jun 17 07:22:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aggeler Fabian X-Patchwork-Id: 360361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id F331E14007B for ; Tue, 17 Jun 2014 17:23:27 +1000 (EST) Received: from localhost ([::1]:47855 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwnjp-0007QL-RR for incoming@patchwork.ozlabs.org; Tue, 17 Jun 2014 03:23:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwnjT-00078o-P2 for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:23:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WwnjN-0007uk-2H for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:23:03 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:44031) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwnjM-0007uf-OM for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:22:56 -0400 Received: from CAS11.d.ethz.ch (172.31.38.211) by edge20.ethz.ch (82.130.99.26) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 17 Jun 2014 09:22:51 +0200 Received: from MBX12.d.ethz.ch ([fe80::fcbd:f3f9:2031:cf24]) by CAS11.d.ethz.ch ([fe80::ecc9:4e2d:b26b:1614%10]) with mapi id 14.03.0195.001; Tue, 17 Jun 2014 09:22:55 +0200 From: "Aggeler Fabian" To: Greg Bellows Thread-Topic: [PATCH v3 02/32] target-arm: move Aarch32 SCR into security reglist Thread-Index: AQHPhQdyG/Q9pLQpQEeaImRTU/Xd25tt5myAgAbn5gA= Date: Tue, 17 Jun 2014 07:22:53 +0000 Message-ID: References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> <1402444514-19658-3-git-send-email-aggelerf@ethz.ch> In-Reply-To: Accept-Language: en-US, de-CH Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [178.198.140.227] Content-ID: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 82.130.99.26 Cc: Peter Maydell , Peter Crosthwaite , QEMU Developers , Sergey Fedorov , "Edgar E. Iglesias" , Christoffer Dall Subject: Re: [Qemu-devel] [PATCH v3 02/32] target-arm: move Aarch32 SCR into security reglist X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On 12 Jun 2014, at 23:55, Greg Bellows > wrote: Conflict with Edgar's changes around the name of the security register group v8_el3_cp_reginfo vs. security_cp_reginfo. Given that there is a difference between the v7 regs and their v8 equivalents such as encoding, I propose we create 2 separate groups, but map them to the same storage where applicable. This somewhat follows on the SCR mapping discussion. That’s actually what I was trying to do here. I separated Aarch32 Security Extension registers into a separate group. They do map to the same storage already in this patch. I guess we could rename the group to v8_el3_a32_cp_reginfo or something like this. What do you think? On 10 June 2014 18:54, Fabian Aggeler > wrote: Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving Aarch32 SCR into Security Extension register group. Signed-off-by: Sergey Fedorov > Signed-off-by: Fabian Aggeler > --- target-arm/helper.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 1.8.3.2 diff --git a/target-arm/helper.c b/target-arm/helper.c index e157cc2..d8d6637 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -792,9 +792,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), .resetvalue = 0 }, - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), - .resetvalue = 0, }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2216,6 +2213,13 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo security_cp_reginfo[] = { + { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), + .resetvalue = 0, }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2479,6 +2483,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + define_arm_cp_regs(cpu, security_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new