From patchwork Tue Nov 4 09:12:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hu Tao X-Patchwork-Id: 406479 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 36B791400B8 for ; Tue, 4 Nov 2014 20:16:28 +1100 (AEDT) Received: from localhost ([::1]:39320 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlaDy-0007hc-2i for incoming@patchwork.ozlabs.org; Tue, 04 Nov 2014 04:16:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36426) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlaDL-0006hz-4a for qemu-devel@nongnu.org; Tue, 04 Nov 2014 04:15:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlaDE-00069W-82 for qemu-devel@nongnu.org; Tue, 04 Nov 2014 04:15:47 -0500 Received: from [59.151.112.132] (port=19174 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlaDD-00067y-P3 for qemu-devel@nongnu.org; Tue, 04 Nov 2014 04:15:40 -0500 X-IronPort-AV: E=Sophos;i="5.04,845,1406563200"; d="scan'208";a="42818307" Received: from localhost (HELO edo.cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 04 Nov 2014 17:12:26 +0800 Received: from G08CNEXCHPEKD03.g08.fujitsu.local (localhost.localdomain [127.0.0.1]) by edo.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id sA49FQKu021432; Tue, 4 Nov 2014 17:15:26 +0800 Received: from localhost.localdomain (10.167.226.102) by G08CNEXCHPEKD03.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.181.6; Tue, 4 Nov 2014 17:15:38 +0800 From: Hu Tao To: Date: Tue, 4 Nov 2014 17:12:15 +0800 Message-ID: <91ab11d98bee9cae97f46f78cc8935451bda77b8.1415091929.git.hutao@cn.fujitsu.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.226.102] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Cc: "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH 4/5] pci: remove the limit parameter of pci_host_config_read_common X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since the limit parameter is always set to the size of pci device's configuration space, and we can determine the size from the type of pci device. Signed-off-by: Hu Tao --- hw/pci/pci_host.c | 15 +++++++++++---- hw/pci/pcie_host.c | 9 +-------- hw/ppc/spapr_pci.c | 3 +-- include/hw/pci/pci_host.h | 2 +- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 406c747..937660c 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -58,12 +58,20 @@ void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, } uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, - uint32_t limit, uint32_t len) + uint32_t len) { + uint32_t limit = pci_config_size(pci_dev); uint32_t ret; assert(len <= 4); - ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); + + if (limit <= addr) { + /* conventional pci device can be behind pcie-to-pci bridge. + 256 <= addr < 4K has no effects. */ + ret = ~0x0; + } else { + ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); + } trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn), addr, ret); @@ -95,8 +103,7 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) return ~0x0; } - val = pci_host_config_read_common(pci_dev, config_addr, - PCI_CONFIG_SPACE_SIZE, len); + val = pci_host_config_read_common(pci_dev, config_addr, len); PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", __func__, pci_dev->name, config_addr, val, len); diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index 3db038f..cf8587b 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -62,19 +62,12 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); uint32_t addr; - uint32_t limit; if (!pci_dev) { return ~0x0; } addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr); - limit = pci_config_size(pci_dev); - if (limit <= addr) { - /* conventional pci device can be behind pcie-to-pci bridge. - 256 <= addr < 4K has no effects. */ - return ~0x0; - } - return pci_host_config_read_common(pci_dev, addr, limit, len); + return pci_host_config_read_common(pci_dev, addr, len); } static const MemoryRegionOps pcie_mmcfg_ops = { diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index ad0da7f..7f38117 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -105,8 +105,7 @@ static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, return; } - val = pci_host_config_read_common(pci_dev, addr, - pci_config_size(pci_dev), size); + val = pci_host_config_read_common(pci_dev, addr, size); rtas_st(rets, 0, RTAS_OUT_SUCCESS); rtas_st(rets, 1, val); diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index ba31595..4a79945 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -60,7 +60,7 @@ typedef struct PCIHostBridgeClass { void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, uint32_t limit, uint32_t val, uint32_t len); uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, - uint32_t limit, uint32_t len); + uint32_t len); void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);