From patchwork Tue Oct 25 14:00:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juan Quintela X-Patchwork-Id: 121702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AEF55B6F70 for ; Wed, 26 Oct 2011 01:19:04 +1100 (EST) Received: from localhost ([::1]:59499 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RIhqH-0002nV-RA for incoming@patchwork.ozlabs.org; Tue, 25 Oct 2011 10:19:01 -0400 Received: from eggs.gnu.org ([140.186.70.92]:40432) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RIhq8-0002mn-PV for qemu-devel@nongnu.org; Tue, 25 Oct 2011 10:18:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RIhq3-0004UT-EK for qemu-devel@nongnu.org; Tue, 25 Oct 2011 10:18:52 -0400 Received: from mx1.redhat.com ([209.132.183.28]:14530) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RIhb1-0002Cq-Cf for qemu-devel@nongnu.org; Tue, 25 Oct 2011 10:03:17 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p9PE3AGW010565 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 25 Oct 2011 10:03:10 -0400 Received: from neno.neno. (ovpn-116-28.ams2.redhat.com [10.36.116.28]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p9PE25Zp028141; Tue, 25 Oct 2011 10:03:06 -0400 From: Juan Quintela To: qemu-devel@nongnu.org Date: Tue, 25 Oct 2011 16:00:57 +0200 Message-Id: <8ea941d8252f36246b44091a17744d6417b00ae8.1319550280.git.quintela@redhat.com> In-Reply-To: References: In-Reply-To: References: X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 209.132.183.28 Cc: Peter Maydell , aliguori@us.ibm.com, Paul Brook Subject: [Qemu-devel] [PATCH 23/25] arm: save always 32 fpu registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This way, we fix a bug (we were overwritten the 16 first registers on load), and we don't need to check for ARM_FEATUR_VPF3, we always send the 32 registers. Signed-off-by: Juan Quintela CC: Paul Brook CC: Peter Maydell --- target-arm/cpu.h | 2 +- target-arm/machine.c | 22 ++-------------------- 2 files changed, 3 insertions(+), 21 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6ab780d..f6d9436 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -446,7 +446,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 4 +#define CPU_SAVE_VERSION 5 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/machine.c b/target-arm/machine.c index 7d4fc54..3a3b325 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -60,7 +60,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->features); if (arm_feature(env, ARM_FEATURE_VFP)) { - for (i = 0; i < 16; i++) { + for (i = 0; i < 32; i++) { CPU_DoubleU u; u.d = env->vfp.regs[i]; qemu_put_be32(f, u.l.upper); @@ -73,15 +73,6 @@ void cpu_save(QEMUFile *f, void *opaque) /* TODO: Should use proper FPSCR access functions. */ qemu_put_be32(f, env->vfp.vec_len); qemu_put_be32(f, env->vfp.vec_stride); - - if (arm_feature(env, ARM_FEATURE_VFP3)) { - for (i = 16; i < 32; i++) { - CPU_DoubleU u; - u.d = env->vfp.regs[i]; - qemu_put_be32(f, u.l.upper); - qemu_put_be32(f, u.l.lower); - } - } } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { @@ -174,7 +165,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->features = qemu_get_be32(f); if (arm_feature(env, ARM_FEATURE_VFP)) { - for (i = 0; i < 16; i++) { + for (i = 0; i < 32; i++) { CPU_DoubleU u; u.l.upper = qemu_get_be32(f); u.l.lower = qemu_get_be32(f); @@ -187,15 +178,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) /* TODO: Should use proper FPSCR access functions. */ env->vfp.vec_len = qemu_get_be32(f); env->vfp.vec_stride = qemu_get_be32(f); - - if (arm_feature(env, ARM_FEATURE_VFP3)) { - for (i = 0; i < 16; i++) { - CPU_DoubleU u; - u.l.upper = qemu_get_be32(f); - u.l.lower = qemu_get_be32(f); - env->vfp.regs[i] = u.d; - } - } } if (arm_feature(env, ARM_FEATURE_IWMMXT)) {