Message ID | 89944e8caeecd85d7136ea53e7b2bbe8aab18222.1618356725.git.alistair.francis@wdc.com |
---|---|
State | New |
Headers | show |
Series | RISC-V: Steps towards running 32-bit guests on | expand |
On Wed, Apr 14, 2021 at 7:34 AM Alistair Francis <alistair.francis@wdc.com> wrote: > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/translate.c | 6 ------ > 1 file changed, 6 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 74636b9db7..ba8fb2cda3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,12 +67,6 @@ typedef struct DisasContext { CPUState *cs; } DisasContext; -#ifdef TARGET_RISCV64 -#define CASE_OP_32_64(X) case X: case glue(X, W) -#else -#define CASE_OP_32_64(X) case X -#endif - static inline bool has_ext(DisasContext *ctx, uint32_t ext) { return ctx->misa & ext;