Message ID | 87vc5nxjm2.fsf@kepler.schwinge.homeip.net |
---|---|
State | New |
Headers | show |
On Sun, 9 Jun 2013, Thomas Schwinge wrote: > In my reading of the relevant documents, the latter change is not correct > for o32, and empirically has "interesting" effects on the glibc math > testsuite, for example. Keeping the FR register unset for o32 I'm > proposing to fix with the following patch: Correct, unless (until?) the -mfp64 o32 ABI extension is implemented for Linux, CP0.Status.FR must remain 0 for o32 programs. > diff --git target-mips/translate.c target-mips/translate.c > index 0a53203..51837d4 100644 > --- target-mips/translate.c > +++ target-mips/translate.c > @@ -15962,10 +15962,12 @@ void cpu_state_reset(CPUMIPSState *env) > if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { > env->CP0_Status |= (1 << CP0St_MX); > } > - /* Enable 64-bit FPU if the target cpu supports it. */ > +# if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) > + /* Enable 64-bit FPU if the target CPU supports it. */ > if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { > env->CP0_Status |= (1 << CP0St_FR); This is not entirely correct, older 64-bit FPUs, i.e. any before the MIPS32/MIPS64 rev. 2 ISA (e.g. R4000, R10000, 5Kf, etc.) won't have the CP1.FIR.F64 bit set; it was only defined at that ISA level because for earlier architecture revisions the type of the FPU could have been inferred from the type of the CPU. Therefore the condition has to be changed, perhaps the best way would simply be just checking in the CP0.Status mask if the FR bit is writable. Also I suppose there must be an else clause here: } else { fprintf(stderr, "A 64-bit FPU required for NewABI emulation\n"); exit(1); or suchlike because the NewABI mandates full 64-bit FPU operation (or the condtion might be changed to an assertion instead and the emulated environment checked elsewhere earlier on, because a 64-bit CPU is required for NewABI operation anyway and a 64-bit CPU can't ever have a 32-bit FPU -- I don't know QEMU well enough to be sure offhand, please check). > } > +# endif > #else > if (env->hflags & MIPS_HFLAG_BMASK) { > /* If the exception was raised from a delay slot, Maciej
Hi!
On Sun, 28 Jul 2013 02:39:23 +0000, Petar Jovanovic <Petar.Jovanovic@imgtec.com> wrote:
> Will there be an update to this patch?
| Switch to 64-bit FPU only for n32 and n64 ABIs, but not o32. Fixup for
| commit 68473f15d4c9948986618f63828825beafcaf1cf.
| [...]
My patch has to be reworked per Maciej's comments,
<http://news.gmane.org/find-root.php?message_id=%3Calpine.DEB.1.10.1306091926470.16287%40tp.orcam.me.uk%3E>,
which I have not yet managed to allocate the time to do, and can't tell
when it's going to happen -- but I still have it on my TODO list.
Grüße,
Thomas
diff --git target-mips/translate.c target-mips/translate.c index 0a53203..51837d4 100644 --- target-mips/translate.c +++ target-mips/translate.c @@ -15962,10 +15962,12 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { env->CP0_Status |= (1 << CP0St_MX); } - /* Enable 64-bit FPU if the target cpu supports it. */ +# if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) + /* Enable 64-bit FPU if the target CPU supports it. */ if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->CP0_Status |= (1 << CP0St_FR); } +# endif #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot,