From patchwork Sat Apr 10 20:22:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 50160 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CA421B7D2E for ; Thu, 15 Apr 2010 00:28:39 +1000 (EST) Received: from localhost ([127.0.0.1]:33471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O23a0-00008Y-M1 for incoming@patchwork.ozlabs.org; Wed, 14 Apr 2010 10:28:36 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O23V9-0007I9-AP for qemu-devel@nongnu.org; Wed, 14 Apr 2010 10:23:35 -0400 Received: from [140.186.70.92] (port=37290 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O23V5-0007Gn-ID for qemu-devel@nongnu.org; Wed, 14 Apr 2010 10:23:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O23V2-0006cA-HH for qemu-devel@nongnu.org; Wed, 14 Apr 2010 10:23:31 -0400 Received: from are.twiddle.net ([75.149.56.221]:43807) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O23V1-0006a6-Oh for qemu-devel@nongnu.org; Wed, 14 Apr 2010 10:23:27 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id 33E0DEC5; Wed, 14 Apr 2010 07:16:20 -0700 (PDT) Message-Id: <85fe4e430e4e65704184145e729afaef5c43d3a9.1271253049.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Sat, 10 Apr 2010 22:22:28 +0200 To: qemu-devel@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 6/6] tcg-hppa: Remove automatically implemented opcodes. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Remove neg, ext8u, ext16u, as requested. Signed-off-by: Richard Henderson --- tcg/hppa/tcg-target.c | 16 ---------------- tcg/hppa/tcg-target.h | 8 +++++--- 2 files changed, 5 insertions(+), 19 deletions(-) diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c index 6536a42..cb605f1 100644 --- a/tcg/hppa/tcg-target.c +++ b/tcg/hppa/tcg-target.c @@ -1431,19 +1431,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_ext16s(s, args[0], args[1]); break; - /* These three correspond exactly to the fallback implementation. - But by including them we reduce the number of TCG ops that - need to be generated, and these opcodes are fairly common. */ - case INDEX_op_neg_i32: - tcg_out_arith(s, args[0], TCG_REG_R0, args[1], INSN_SUB); - break; - case INDEX_op_ext8u_i32: - tcg_out_andi(s, args[0], args[1], 0xff); - break; - case INDEX_op_ext16u_i32: - tcg_out_andi(s, args[0], args[1], 0xffff); - break; - case INDEX_op_brcond_i32: tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]); break; @@ -1550,13 +1537,10 @@ static const TCGTargetOpDef hppa_op_defs[] = { { INDEX_op_bswap16_i32, { "r", "r" } }, { INDEX_op_bswap32_i32, { "r", "r" } }, - { INDEX_op_neg_i32, { "r", "r" } }, { INDEX_op_not_i32, { "r", "r" } }, { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "r" } }, { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, { INDEX_op_brcond_i32, { "rZ", "rJ" } }, { INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } }, diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h index 7e21f1d..a5cc440 100644 --- a/tcg/hppa/tcg-target.h +++ b/tcg/hppa/tcg-target.h @@ -89,15 +89,17 @@ enum { #define TCG_TARGET_HAS_rot_i32 #define TCG_TARGET_HAS_ext8s_i32 #define TCG_TARGET_HAS_ext16s_i32 -#define TCG_TARGET_HAS_ext8u_i32 -#define TCG_TARGET_HAS_ext16u_i32 #define TCG_TARGET_HAS_bswap16_i32 #define TCG_TARGET_HAS_bswap32_i32 #define TCG_TARGET_HAS_not_i32 -#define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 +/* optional instructions automatically implemented */ +#undef TCG_TARGET_HAS_neg_i32 /* sub rd, 0, rs */ +#undef TCG_TARGET_HAS_ext8u_i32 /* and rd, rs, 0xff */ +#undef TCG_TARGET_HAS_ext16u_i32 /* and rd, rs, 0xffff */ + #define TCG_TARGET_HAS_GUEST_BASE /* Note: must be synced with dyngen-exec.h */