diff mbox series

[4/5] hw/riscv: IOMMU: use process identifier from transaction attributes.

Message ID 81df51e9bd547f1826d67834a0d705977d7e1435.1689819032.git.tjeznach@rivosinc.com
State New
Headers show
Series QEMU RISC-V IOMMU Support | expand

Commit Message

Tomasz Jeznach July 20, 2023, 2:32 a.m. UTC 
Use iommu index as process identifier, linking transaction
memory attributes with translation request.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
---
 hw/riscv/riscv-iommu.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index fd271b2988..62525df2e2 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2236,6 +2236,12 @@  static void riscv_iommu_realize(DeviceState *dev, Error **errp)
     /* Report QEMU target physical address space limits */
     s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, TARGET_PHYS_ADDR_SPACE_BITS);
 
+    /* Restricted to the size of MemTxAttrs.pasid field. */
+    if (s->cap & RISCV_IOMMU_CAP_PD8) {
+        MemTxAttrs attrs = { .pasid = ~0 };
+        s->pasid_bits = ctz32(~((unsigned)attrs.pasid));
+    }
+
     /* Adjust reported PD capabilities */
     if (s->pasid_bits < 20) {
         s->cap &= ~RISCV_IOMMU_CAP_PD20;
@@ -2506,12 +2512,13 @@  void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
 static int riscv_iommu_memory_region_index(IOMMUMemoryRegion *iommu_mr,
     MemTxAttrs attrs)
 {
-    return RISCV_IOMMU_NOPASID;
+    return attrs.unspecified ? RISCV_IOMMU_NOPASID : (int)attrs.pasid;
 }
 
 static int riscv_iommu_memory_region_index_len(IOMMUMemoryRegion *iommu_mr)
 {
-    return 1;
+    RISCVIOMMUSpace *as = container_of(iommu_mr, RISCVIOMMUSpace, iova_mr);
+    return 1 << as->iommu->pasid_bits;
 }
 
 static void riscv_iommu_memory_region_init(ObjectClass *klass, void *data)