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SRVR:BL2FFO11HUB022; BCL:0; PCL:0; RULEID:; SRVR:BL2FFO11HUB022; X-Forefront-PRVS: 05177D47DC X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2015 12:12:21.8720 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2FFO11HUB022 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 157.56.110.54 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, zach.pfeffer@xilinx.com, alistair.francis@xilinx.com, michals@xilinx.com, alex.bennee@linaro.org Subject: [Qemu-devel] [PATCH target-arm v3 07/15] net: cadence_gem: Split state struct and type into header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To allow using the device with modern SoC programming conventions. The state struct needs to be visible to embed the device in SoC containers. Reviewed-by: Alistair Francis Signed-off-by: Peter Crosthwaite --- changed since v1: Fix /* Public */ comment spacing (Alistair review) hw/net/cadence_gem.c | 43 +------------------------------------- include/hw/net/cadence_gem.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 42 deletions(-) create mode 100644 include/hw/net/cadence_gem.h diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 5994306..dafe914 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -24,8 +24,7 @@ #include /* For crc32 */ -#include "hw/sysbus.h" -#include "net/net.h" +#include "hw/net/cadence_gem.h" #include "net/checksum.h" #ifdef CADENCE_GEM_ERR_DEBUG @@ -141,8 +140,6 @@ #define GEM_DESCONF6 (0x00000294/4) #define GEM_DESCONF7 (0x00000298/4) -#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ - /*****************************************/ #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ @@ -349,44 +346,6 @@ static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) desc[1] |= R_DESC_1_RX_SAR_MATCH; } -#define TYPE_CADENCE_GEM "cadence_gem" -#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM) - -typedef struct CadenceGEMState { - SysBusDevice parent_obj; - - MemoryRegion iomem; - NICState *nic; - NICConf conf; - qemu_irq irq; - - /* GEM registers backing store */ - uint32_t regs[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are write only */ - uint32_t regs_wo[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are read only */ - uint32_t regs_ro[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are clear on read */ - uint32_t regs_rtc[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are write 1 to clear */ - uint32_t regs_w1c[CADENCE_GEM_MAXREG]; - - /* PHY registers backing store */ - uint16_t phy_regs[32]; - - uint8_t phy_loop; /* Are we in phy loopback? */ - - /* The current DMA descriptor pointers */ - uint32_t rx_desc_addr; - uint32_t tx_desc_addr; - - uint8_t can_rx_state; /* Debug only */ - - unsigned rx_desc[2]; - - bool sar_active[4]; -} CadenceGEMState; - /* The broadcast MAC address: 0xFFFFFFFFFFFF */ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h new file mode 100644 index 0000000..12de820 --- /dev/null +++ b/include/hw/net/cadence_gem.h @@ -0,0 +1,49 @@ +#ifndef CADENCE_GEM_H_ + +#define TYPE_CADENCE_GEM "cadence_gem" +#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM) + +#include "net/net.h" +#include "hw/sysbus.h" + +#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ + +typedef struct CadenceGEMState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + NICState *nic; + NICConf conf; + qemu_irq irq; + + /* GEM registers backing store */ + uint32_t regs[CADENCE_GEM_MAXREG]; + /* Mask of register bits which are write only */ + uint32_t regs_wo[CADENCE_GEM_MAXREG]; + /* Mask of register bits which are read only */ + uint32_t regs_ro[CADENCE_GEM_MAXREG]; + /* Mask of register bits which are clear on read */ + uint32_t regs_rtc[CADENCE_GEM_MAXREG]; + /* Mask of register bits which are write 1 to clear */ + uint32_t regs_w1c[CADENCE_GEM_MAXREG]; + + /* PHY registers backing store */ + uint16_t phy_regs[32]; + + uint8_t phy_loop; /* Are we in phy loopback? */ + + /* The current DMA descriptor pointers */ + uint32_t rx_desc_addr; + uint32_t tx_desc_addr; + + uint8_t can_rx_state; /* Debug only */ + + unsigned rx_desc[2]; + + bool sar_active[4]; +} CadenceGEMState; + +#define CADENCE_GEM_H_ +#endif