From patchwork Mon Mar 4 09:01:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 224642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B9D112C02F2 for ; Mon, 4 Mar 2013 20:05:53 +1100 (EST) Received: from localhost ([::1]:47074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRLD-0007j4-GV for incoming@patchwork.ozlabs.org; Mon, 04 Mar 2013 04:05:51 -0500 Received: from eggs.gnu.org ([208.118.235.92]:37478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRKm-0007dI-Ks for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:05:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCRKi-0007gZ-JT for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:05:24 -0500 Received: from mail-pa0-f50.google.com ([209.85.220.50]:44466) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRKi-0007gQ-E3 for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:05:20 -0500 Received: by mail-pa0-f50.google.com with SMTP id fa11so3027845pad.9 for ; Mon, 04 Mar 2013 01:05:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:x-gm-message-state; bh=7adASTjMmHWUv+T/aPxVF8hfnida0ZqLkp5jkvfH3Bo=; b=XU4K2r7rPDhSSfnS86VKLN52zd+IdS/voHkYmKQRa6sDcwHbu3GqvuAWtOf/vvZIi4 DQpUfASrYul+MHksEqbtWFWX3jA2lqGg9p5ZeRiVj79z6MW/9fJ3N/6qNTmc4k79huxX rqgAiKNHdkftqGl32lXDs1CIijAqBWvkPBWC/hTLcuBQcCJuiBKJQx0GSKsSETobrpq4 H8iVp3xV7LoCwTOybfCGgablmxCWvXK8rC8xbRO1bZZFABpNnHPhLW5i5xa+jvLSOvhG pknpWVh9BqI1pGxBYV9IdyKm30l0ADLDy7FQuK72crXsq7Tvvu13UE/AiBSyLIMeMWHH 8Zkg== X-Received: by 10.68.28.194 with SMTP id d2mr26673358pbh.215.1362387919762; Mon, 04 Mar 2013 01:05:19 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id j7sm23206633pay.10.2013.03.04.01.05.09 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 04 Mar 2013 01:05:18 -0800 (PST) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 4 Mar 2013 19:01:36 +1000 Message-Id: <7e289d2451695cfa9bea161ce19165f746e358ff.1362387546.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQmVKnJCMaFLUOc8iyTC+v0Ap/+kXrukK8LPKJKN/ZkWh1rbrE2oHje7Yib29BAYUqEXjPHd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.50 Cc: Peter Crosthwaite , andreas.faerber@suse.de, dantesu@faraday-tech.com Subject: [Qemu-devel] [RFC PATCH v1 4/7] sun4m: Use halting API to halt/unhalt CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Example for a change pattern that could be applied to use the halting API rather than directly modifying the CPU halted bit. Untested RFC. Signed-off-by: Peter Crosthwaite --- hw/sun4m.c | 24 ++++++++++++------------ 1 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/sun4m.c b/hw/sun4m.c index d83d42c..b544782 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -261,8 +261,9 @@ static void cpu_kick_irq(SPARCCPU *cpu) { CPUSPARCState *env = &cpu->env; CPUState *cs = CPU(cpu); + DeviceState *d = DEVICE(cpu); - cs->halted = 0; + device_unhalt(d); cpu_check_irqs(env); qemu_cpu_kick(cs); } @@ -289,20 +290,19 @@ static void dummy_cpu_set_irq(void *opaque, int irq, int level) static void main_cpu_reset(void *opaque) { - SPARCCPU *cpu = opaque; - CPUState *cs = CPU(cpu); + DeviceState *d = DEVICE(opaque); - cpu_reset(cs); - cs->halted = 0; + device_reset(d); + device_unhalt(d); } static void secondary_cpu_reset(void *opaque) { - SPARCCPU *cpu = opaque; - CPUState *cs = CPU(cpu); + DeviceState *d = DEVICE(opaque); + + device_reset(d); + device_halt(d); - cpu_reset(cs); - cs->halted = 1; } static void cpu_halt_signal(void *opaque, int irq, int level) @@ -833,7 +833,7 @@ static const TypeInfo ram_info = { static void cpu_devinit(const char *cpu_model, unsigned int id, uint64_t prom_addr, qemu_irq **cpu_irqs) { - CPUState *cs; + DeviceState *d; SPARCCPU *cpu; CPUSPARCState *env; @@ -849,8 +849,8 @@ static void cpu_devinit(const char *cpu_model, unsigned int id, qemu_register_reset(main_cpu_reset, cpu); } else { qemu_register_reset(secondary_cpu_reset, cpu); - cs = CPU(cpu); - cs->halted = 1; + d = DEVICE(cpu); + device_halt(DEIVCE(cpu)); } *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); env->prom_addr = prom_addr;