From patchwork Tue Jun 22 08:57:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 56440 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5AD92B6EF1 for ; Tue, 22 Jun 2010 19:20:08 +1000 (EST) Received: from localhost ([127.0.0.1]:34736 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OQzeH-0006j4-DW for incoming@patchwork.ozlabs.org; Tue, 22 Jun 2010 05:20:05 -0400 Received: from [140.186.70.92] (port=35007 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OQzPh-0007d3-Sk for qemu-devel@nongnu.org; Tue, 22 Jun 2010 05:05:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OQzMS-0002sN-Bs for qemu-devel@nongnu.org; Tue, 22 Jun 2010 05:01:41 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:55547) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OQzMR-0002rk-Rm for qemu-devel@nongnu.org; Tue, 22 Jun 2010 05:01:40 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id C63BD10742C; Tue, 22 Jun 2010 18:01:38 +0900 (JST) Received: (nullmailer pid 28814 invoked by uid 1000); Tue, 22 Jun 2010 08:57:53 -0000 From: Isaku Yamahata To: seabios@seabios.org Date: Tue, 22 Jun 2010 17:57:47 +0900 Message-Id: <7c80df8b2ae3506811eba079ef981045b4951550.1277196704.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: stefano.stabellini@eu.citrix.com, jan.kiszka@siemens.com, mst@redhat.com, allen.m.kay@intel.com, qemu-devel@nongnu.org, yamahata@valinux.co.jp, jean.guyader@gmail.com Subject: [Qemu-devel] [PATCH v2 2/8] seabios: pciinit: factor out pci bar region allocation logic. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org factor out pci bar region allocation logic. Signed-off-by: Isaku Yamahata --- src/pciinit.c | 84 ++++++++++++++++++++++++++++++++------------------------- 1 files changed, 47 insertions(+), 37 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index 0556ee2..488c77b 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -37,6 +37,50 @@ static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr) dprintf(1, "region %d: 0x%08x\n", region_num, addr); } +static void pci_bios_allocate_region(u16 bdf, int region_num) +{ + u32 *paddr; + int ofs; + if (region_num == PCI_ROM_SLOT) + ofs = PCI_ROM_ADDRESS; + else + ofs = PCI_BASE_ADDRESS_0 + region_num * 4; + + u32 old = pci_config_readl(bdf, ofs); + u32 mask; + if (region_num == PCI_ROM_SLOT) { + mask = PCI_ROM_ADDRESS_MASK; + pci_config_writel(bdf, ofs, mask); + } else { + if (old & PCI_BASE_ADDRESS_SPACE_IO) + mask = PCI_BASE_ADDRESS_IO_MASK; + else + mask = PCI_BASE_ADDRESS_MEM_MASK; + pci_config_writel(bdf, ofs, ~0); + } + u32 val = pci_config_readl(bdf, ofs); + pci_config_writel(bdf, ofs, old); + + if (val != 0) { + u32 size = (~(val & mask)) + 1; + if (val & PCI_BASE_ADDRESS_SPACE_IO) + paddr = &pci_bios_io_addr; + else + paddr = &pci_bios_mem_addr; + *paddr = ALIGN(*paddr, size); + pci_set_io_region_addr(bdf, region_num, *paddr); + *paddr += size; + } +} + +static void pci_bios_allocate_regions(u16 bdf) +{ + int i; + for (i = 0; i < PCI_NUM_REGIONS; i++) { + pci_bios_allocate_region(bdf, i); + } +} + /* return the global irq number corresponding to a given device irq pin. We could also use the bus number to have a more precise mapping. */ @@ -78,8 +122,7 @@ static void pci_bios_init_bridges(u16 bdf) static void pci_bios_init_device(u16 bdf) { int class; - u32 *paddr; - int i, pin, pic_irq, vendor_id, device_id; + int pin, pic_irq, vendor_id, device_id; class = pci_config_readw(bdf, PCI_CLASS_DEVICE); vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID); @@ -94,7 +137,7 @@ static void pci_bios_init_device(u16 bdf) /* PIIX3/PIIX4 IDE */ pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1 - goto default_map; + pci_bios_allocate_regions(bdf); } else { /* IDE: we map it as in ISA mode */ pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE); @@ -121,41 +164,8 @@ static void pci_bios_init_device(u16 bdf) } break; default: - default_map: /* default memory mappings */ - for (i = 0; i < PCI_NUM_REGIONS; i++) { - int ofs; - if (i == PCI_ROM_SLOT) - ofs = PCI_ROM_ADDRESS; - else - ofs = PCI_BASE_ADDRESS_0 + i * 4; - - u32 old = pci_config_readl(bdf, ofs); - u32 mask; - if (i == PCI_ROM_SLOT) { - mask = PCI_ROM_ADDRESS_MASK; - pci_config_writel(bdf, ofs, mask); - } else { - if (old & PCI_BASE_ADDRESS_SPACE_IO) - mask = PCI_BASE_ADDRESS_IO_MASK; - else - mask = PCI_BASE_ADDRESS_MEM_MASK; - pci_config_writel(bdf, ofs, ~0); - } - u32 val = pci_config_readl(bdf, ofs); - pci_config_writel(bdf, ofs, old); - - if (val != 0) { - u32 size = (~(val & mask)) + 1; - if (val & PCI_BASE_ADDRESS_SPACE_IO) - paddr = &pci_bios_io_addr; - else - paddr = &pci_bios_mem_addr; - *paddr = ALIGN(*paddr, size); - pci_set_io_region_addr(bdf, i, *paddr); - *paddr += size; - } - } + pci_bios_allocate_regions(bdf); break; }