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[37.6.163.245]) by smtp.gmail.com with ESMTPSA id cu3-20020a170906ba8300b00a3d014fa12esm3747876ejd.196.2024.02.20.00.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 00:53:20 -0800 (PST) From: Manos Pitsidianakis To: qemu-trivial@nongnu.org Cc: qemu-devel@nongnu.org, Michael Tokarev , Jonathan Cameron , Fan Ni Subject: [PATCH v1 11/21] hw/cxl/cxl_device.h: correct typos Date: Tue, 20 Feb 2024 10:52:18 +0200 Message-Id: <76ecf49e448d00c6b1b09446c832e007dd1f811a.1708419115.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Correct typos automatically found with the `typos` tool Signed-off-by: Manos Pitsidianakis --- include/hw/cxl/cxl_device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index d8e184c4ba..279b276bda 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -268,7 +268,7 @@ void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type, /* * Helper macro to initialize capability headers for CXL devices. * - * In CXL r3.1 Section 8.2.8.2: CXL Device Capablity Header Register, this is + * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is * listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register * Interface, it says: * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that @@ -276,7 +276,7 @@ void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type, * > followed, the behavior is undefined. * * > To illustrate how the fields fit together, the layouts ... are shown as - * > wider than a 64 bit register. Implemenations are expected to use any size + * > wider than a 64 bit register. Implementations are expected to use any size * > accesses for this information up to 64 bits without lost of functionality * * Here we've chosen to make it 4 dwords.