From patchwork Wed Sep 28 11:00:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 116769 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E011DB6F7D for ; Wed, 28 Sep 2011 22:02:02 +1000 (EST) Received: from localhost ([::1]:34215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R8ru8-0007vl-5o for incoming@patchwork.ozlabs.org; Wed, 28 Sep 2011 07:02:20 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R8rtE-00051F-6Q for qemu-devel@nongnu.org; Wed, 28 Sep 2011 07:01:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R8rt2-0004F4-GO for qemu-devel@nongnu.org; Wed, 28 Sep 2011 07:01:23 -0400 Received: from goliath.siemens.de ([192.35.17.28]:20930) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R8rt2-0004Dp-7m for qemu-devel@nongnu.org; Wed, 28 Sep 2011 07:01:12 -0400 Received: from mail1.siemens.de (localhost [127.0.0.1]) by goliath.siemens.de (8.13.6/8.13.6) with ESMTP id p8SB1AIK015407; Wed, 28 Sep 2011 13:01:10 +0200 Received: from mchn199C.mchp.siemens.de ([139.25.109.49]) by mail1.siemens.de (8.13.6/8.13.6) with ESMTP id p8SB18W0017664; Wed, 28 Sep 2011 13:01:10 +0200 From: Jan Kiszka To: Anthony Liguori , qemu-devel Date: Wed, 28 Sep 2011 13:00:58 +0200 Message-Id: <6fcea37212a2baec80a7d1d79a777359a8ca3674.1317207666.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 192.35.17.28 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 12/22] i8259: Switch to per-PIC IRQ update X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This converts pic_update_irq to work against a single PIC instead of the complete cascade. Along this change, the required update after pic_set_irq1 is now moved into that function. Signed-off-by: Jan Kiszka --- hw/i8259.c | 59 ++++++++++++++++++++--------------------------------------- 1 files changed, 20 insertions(+), 39 deletions(-) diff --git a/hw/i8259.c b/hw/i8259.c index 3498c6b..53b86dd 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -118,39 +118,19 @@ static int pic_get_irq(PicState *s) } } -static void pic_set_irq1(PicState *s, int irq, int level); - -/* raise irq to CPU if necessary. must be called every time the active - irq may change */ -static void pic_update_irq(PicState2 *s) +/* Update INT output. Must be called every time the output may have changed. */ +static void pic_update_irq(PicState *s) { - int irq2, irq; - - /* first look at slave pic */ - irq2 = pic_get_irq(&s->pics[1]); - if (irq2 >= 0) { - /* if irq request by slave pic, signal master PIC */ - pic_set_irq1(&s->pics[0], 2, 1); - pic_set_irq1(&s->pics[0], 2, 0); - } - /* look at requested irq */ - irq = pic_get_irq(&s->pics[0]); - if (irq >= 0) { -#if defined(DEBUG_PIC) - { - int i; - for(i = 0; i < 2; i++) { - printf("pic%d: imr=%x irr=%x padd=%d\n", - i, s->pics[i].imr, s->pics[i].irr, - s->pics[i].priority_add); + int irq; - } - } - printf("pic: cpu_interrupt\n"); -#endif - qemu_irq_raise(s->pics[0].int_out); + irq = pic_get_irq(s); + if (irq >= 0) { + DPRINTF("pic%d: imr=%x irr=%x padd=%d\n", + s == &s->pics_state->pics[0] ? 0 : 1, s->imr, s->irr, + s->priority_add); + qemu_irq_raise(s->int_out); } else { - qemu_irq_lower(s->pics[0].int_out); + qemu_irq_lower(s->int_out); } } @@ -179,6 +159,7 @@ static void pic_set_irq1(PicState *s, int irq, int level) s->last_irr &= ~mask; } } + pic_update_irq(s); } #ifdef DEBUG_IRQ_LATENCY @@ -205,7 +186,6 @@ static void i8259_set_irq(void *opaque, int irq, int level) } #endif pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); - pic_update_irq(s); } /* acknowledge interrupt 'irq' */ @@ -220,6 +200,7 @@ static void pic_intack(PicState *s, int irq) /* We don't clear a level sensitive interrupt here */ if (!(s->elcr & (1 << irq))) s->irr &= ~(1 << irq); + pic_update_irq(s); } int pic_read_irq(PicState2 *s) @@ -246,7 +227,6 @@ int pic_read_irq(PicState2 *s) irq = 7; intno = s->pics[0].irq_base + irq; } - pic_update_irq(s); #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY) if (irq == 2) { @@ -283,7 +263,7 @@ static void pic_reset(void *opaque) s->init4 = 0; s->single_mode = 0; /* Note: ELCR is not reset */ - pic_update_irq(s->pics_state); + pic_update_irq(s); } static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, @@ -326,23 +306,23 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, s->isr &= ~(1 << irq); if (cmd == 5) s->priority_add = (irq + 1) & 7; - pic_update_irq(s->pics_state); + pic_update_irq(s); } break; case 3: irq = val & 7; s->isr &= ~(1 << irq); - pic_update_irq(s->pics_state); + pic_update_irq(s); break; case 6: s->priority_add = (val + 1) & 7; - pic_update_irq(s->pics_state); + pic_update_irq(s); break; case 7: irq = val & 7; s->isr &= ~(1 << irq); s->priority_add = (irq + 1) & 7; - pic_update_irq(s->pics_state); + pic_update_irq(s); break; default: /* no operation */ @@ -354,7 +334,7 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, case 0: /* normal mode */ s->imr = val; - pic_update_irq(s->pics_state); + pic_update_irq(s); break; case 1: s->irq_base = val & 0xf8; @@ -390,8 +370,9 @@ static uint32_t pic_poll_read(PicState *s) } s->irr &= ~(1 << ret); s->isr &= ~(1 << ret); - if (slave || ret != 2) - pic_update_irq(s->pics_state); + if (slave || ret != 2) { + pic_update_irq(s); + } } else { ret = 0x07; }