From patchwork Thu Jul 2 14:14:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Fedin X-Patchwork-Id: 490658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AD523140157 for ; Fri, 3 Jul 2015 00:20:32 +1000 (AEST) Received: from localhost ([::1]:36868 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAfLq-0005wS-PG for incoming@patchwork.ozlabs.org; Thu, 02 Jul 2015 10:20:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36712) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAfFr-0003nd-Rf for qemu-devel@nongnu.org; Thu, 02 Jul 2015 10:14:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZAfFo-0003RK-Ol for qemu-devel@nongnu.org; Thu, 02 Jul 2015 10:14:19 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:35598) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAfFo-0003RA-Fj for qemu-devel@nongnu.org; Thu, 02 Jul 2015 10:14:16 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NQV00J8567RU7B0@mailout3.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 02 Jul 2015 15:14:15 +0100 (BST) X-AuditID: cbfec7f4-f79c56d0000012ee-51-55954737e5b7 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 34.35.04846.73745955; Thu, 2 Jul 2015 15:14:15 +0100 (BST) Received: from localhost ([106.109.131.169]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NQV00HFX67QLD90@eusync2.samsung.com>; Thu, 02 Jul 2015 15:14:15 +0100 (BST) From: Pavel Fedin To: qemu-devel@nongnu.org Date: Thu, 02 Jul 2015 17:14:06 +0300 Message-id: <6f1991eed31e0a7fca192eb3640abd06fe07dad6.1435844519.git.p.fedin@samsung.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-reply-to: References: In-reply-to: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjluLIzCtJLcpLzFFi42I5/e/4FV1z96mhBm2zRCzmnHnAYnG8dweL A5PHnWt72DyeXNvMFMAUxWWTkpqTWZZapG+XwJVxp301U8Ed+4qHXdPYGhjPG3QxcnJICJhI fH37kgXCFpO4cG89WxcjF4eQwFJGiePtv1khnG+MEms7W8Gq2ATUJU5//QBmiwhISvzuOs0M UsQs8IhR4lrbOWaQhLCAhcTtHefYQWwWAVWJCQ86GEFsXoFoifaLy5gh1mlILPoyhw3E5hQw l7j+tAmsXkjATOLgzTZGXOITGPkXMDKsYhRNLU0uKE5KzzXUK07MLS7NS9dLzs/dxAgJnS87 GBcfszrEKMDBqMTDu6JmSqgQa2JZcWXuIUYJDmYlEd4tllNDhXhTEiurUovy44tKc1KLDzFK c7AoifPO3fU+REggPbEkNTs1tSC1CCbLxMEp1cBYmN48a1fOD/awms92E1ZVTo1L37SmuqFi jeD/uTwv/hwJ8+GLsvGZ9r8o/PX5uNIf+fe271o7/abxp5oplyu4fi98uc2Vw9Nnovznjfx6 ypxOU9MyTiftVWqKO2IqttDob+KDuaozN174LnHWdYJu1a66pgeG5w2lV9zeP8HVMuzhmh6H Bz9llFiKMxINtZiLihMBEXdk+BkCAAA= X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 210.118.77.13 Cc: Peter Maydell , Shlomo Pongratz , Shlomo Pongratz , Christoffer Dall , Eric Auger Subject: [Qemu-devel] [PATCH v4 8/9] Initial implementation of vGICv3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Get/put routines are missing, live migration is not possible. Signed-off-by: Pavel Fedin --- hw/intc/Makefile.objs | 1 + hw/intc/arm_gicv3_kvm.c | 203 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 hw/intc/arm_gicv3_kvm.c diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 6c2b136..22c8814 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -18,6 +18,7 @@ common-obj-$(CONFIG_OPENPIC) += openpic.o obj-$(CONFIG_APIC) += apic.o apic_common.o obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o +obj-$(CONFIG_ARM_GIC_KVM) += arm_gicv3_kvm.o obj-$(CONFIG_STELLARIS) += armv7m_nvic.o obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o obj-$(CONFIG_GRLIB) += grlib_irqmp.o diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c new file mode 100644 index 0000000..46bf7a6 --- /dev/null +++ b/hw/intc/arm_gicv3_kvm.c @@ -0,0 +1,203 @@ +/* + * ARM Generic Interrupt Controller using KVM in-kernel support + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * Written by Pavel Fedin + * Based on vGICv2 code by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "hw/sysbus.h" +#include "sysemu/kvm.h" +#include "kvm_arm.h" +#include "gicv3_internal.h" +#include "vgic_common.h" + +#ifdef DEBUG_GICV3_KVM +static const int debug_gicv3_kvm = 1; +#else +static const int debug_gicv3_kvm = 0; +#endif + +#define DPRINTF(fmt, ...) do { \ + if (debug_gicv3_kvm) { \ + printf("kvm_gicv3: " fmt , ## __VA_ARGS__); \ + } \ + } while (0) + +#define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" +#define KVM_ARM_GICV3(obj) \ + OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3) +#define KVM_ARM_GICV3_CLASS(klass) \ + OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3) +#define KVM_ARM_GICV3_GET_CLASS(obj) \ + OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3) + +typedef struct KVMARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + void (*parent_reset)(DeviceState *dev); +} KVMARMGICv3Class; + +static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) +{ + GICv3State *s = (GICv3State *)opaque; + + kvm_arm_gic_set_irq(s->num_irq, irq, level); +} + +static void kvm_arm_gicv3_put(GICv3State *s) +{ + /* TODO */ + DPRINTF("Cannot put kernel gic state, no kernel interface\n"); +} + +static void kvm_arm_gicv3_get(GICv3State *s) +{ + /* TODO */ + DPRINTF("Cannot get kernel gic state, no kernel interface\n"); +} + +static void kvm_arm_gicv3_reset(DeviceState *dev) +{ + GICv3State *s = ARM_GICV3_COMMON(dev); + KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); + + DPRINTF("Reset\n"); + + kgc->parent_reset(dev); + kvm_arm_gicv3_put(s); +} + +static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) +{ + int i; + GICv3State *s = KVM_ARM_GICV3(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); + Error *local_err = NULL; + int ret; + + DPRINTF("kvm_arm_gicv3_realize\n"); + + kgc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + i = s->num_irq - GICV3_INTERNAL; + /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. + * GPIO array layout is thus: + * [0..N-1] SPIs + * [N..N+31] PPIs for CPU 0 + * [N+32..N+63] PPIs for CPU 1 + * ... + */ + i += (GICV3_INTERNAL * s->num_cpu); + qdev_init_gpio_in(dev, kvm_arm_gicv3_set_irq, i); + /* We never use our outbound IRQ lines but provide them so that + * we maintain the same interface as the non-KVM GIC. + */ + for (i = 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->parent_irq[i]); + } + for (i = 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->parent_fiq[i]); + } + + /* Try to create the device via the device control API */ + s->dev_fd = -1; + ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); + if (ret >= 0) { + s->dev_fd = ret; + } else if (ret != -ENODEV && ret != -ENOTSUP) { + error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); + return; + } + + if (kvm_gic_supports_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) { + uint32_t numirqs = s->num_irq; + DPRINTF("KVM_DEV_ARM_VGIC_GRP_NR_IRQS = %u\n", numirqs); + kvm_gic_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, + 0, 0, &numirqs, 1); + } + + /* Tell the kernel to complete VGIC initialization now */ + if (kvm_gic_supports_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CTRL_INIT)) { + DPRINTF("KVM_DEV_ARM_VGIC_CTRL_INIT\n"); + kvm_gic_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CTRL_INIT, 0, 0, 1); + } + + /* Distributor */ + memory_region_init_reservation(&s->iomem_dist, OBJECT(s), + "kvm-gicv3_dist", 0x10000); + sysbus_init_mmio(sbd, &s->iomem_dist); + kvm_arm_register_device(&s->iomem_dist, -1, + KVM_DEV_ARM_VGIC_GRP_ADDR, + KVM_VGIC_V3_ADDR_TYPE_DIST, + s->dev_fd); + + /* Nothing much to do with MBI and ITS */ + memory_region_init_reservation(&s->iomem_mbi, OBJECT(s), + "kvm-gicv3_mbi", 0x10000); + sysbus_init_mmio(sbd, &s->iomem_mbi); + memory_region_init_reservation(&s->iomem_its_cntrl, OBJECT(s), + "kvm-gicv3_its_control", 0x10000); + sysbus_init_mmio(sbd, &s->iomem_its_cntrl); + memory_region_init_reservation(&s->iomem_its, OBJECT(s), + "kvm-gicv3_its_translation", 0x10000); + sysbus_init_mmio(sbd, &s->iomem_its); + + /* Redistributor */ + memory_region_init_reservation(&s->iomem_lpi, OBJECT(s), + "kvm-gicv3_lpi", 0x800000); + sysbus_init_mmio(sbd, &s->iomem_lpi); + kvm_arm_register_device(&s->iomem_lpi, -1, + KVM_DEV_ARM_VGIC_GRP_ADDR, + KVM_VGIC_V3_ADDR_TYPE_REDIST, + s->dev_fd); +} + +static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); + KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); + + agcc->pre_save = kvm_arm_gicv3_get; + agcc->post_load = kvm_arm_gicv3_put; + kgc->parent_realize = dc->realize; + kgc->parent_reset = dc->reset; + dc->realize = kvm_arm_gicv3_realize; + dc->reset = kvm_arm_gicv3_reset; +} + +static const TypeInfo kvm_arm_gicv3_info = { + .name = TYPE_KVM_ARM_GICV3, + .parent = TYPE_ARM_GICV3_COMMON, + .instance_size = sizeof(GICv3State), + .class_init = kvm_arm_gicv3_class_init, + .class_size = sizeof(KVMARMGICv3Class), +}; + +static void kvm_arm_gicv3_register_types(void) +{ + type_register_static(&kvm_arm_gicv3_info); +} + +type_init(kvm_arm_gicv3_register_types)