From patchwork Fri Jun 15 09:47:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 165069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9C9A51007E2 for ; Fri, 15 Jun 2012 19:50:10 +1000 (EST) Received: from localhost ([::1]:37229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfTAO-0005gW-IO for incoming@patchwork.ozlabs.org; Fri, 15 Jun 2012 05:50:08 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfTAB-0005g4-1X for qemu-devel@nongnu.org; Fri, 15 Jun 2012 05:50:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SfTA5-0000m4-US for qemu-devel@nongnu.org; Fri, 15 Jun 2012 05:49:54 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:52939) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfTA5-0000l7-2z for qemu-devel@nongnu.org; Fri, 15 Jun 2012 05:49:49 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q5FAQ3m4006937; Fri, 15 Jun 2012 18:26:03 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id 1E48F1460498; Fri, 15 Jun 2012 17:47:58 +0800 (CST) From: Guan Xuetao To: qemu-devel@nongnu.org Date: Fri, 15 Jun 2012 17:47:36 +0800 Message-Id: <6a7dd7552066453f3791b9327df20ffb51611aee.1339753406.git.gxt@mprc.pku.edu.cn> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: blauwirbel@gmail.com, Guan Xuetao , afaerber@suse.de, chenwj@iis.sinica.edu.tw Subject: [Qemu-devel] [PATCHv2 03/13] unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch initializes the cpuid to exactly correct value because linux kernel will check it. Also UC32_CPUID_* are removed. In addition, the exception types are specified in proper situations. Then it could make exceptions generated correctly and timely. Signed-off-by: Guan Xuetao --- cpu-exec.c | 1 + linux-user/main.c | 3 ++- target-unicore32/cpu.c | 25 ++++++++++++++++--------- target-unicore32/cpu.h | 12 +++++------- 4 files changed, 24 insertions(+), 17 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 0344cd5..929b535 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -416,6 +416,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_UNICORE32) if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_asr & ASR_I)) { + env->exception_index = UC32_EXCP_INTR; do_interrupt(env); next_tb = 0; } diff --git a/linux-user/main.c b/linux-user/main.c index 191b750..a394409 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -958,7 +958,8 @@ void cpu_loop(CPUUniCore32State *env) } } break; - case UC32_EXCP_TRAP: + case UC32_EXCP_DTRAP: + case UC32_EXCP_ITRAP: info.si_signo = SIGSEGV; info.si_errno = 0; /* XXX: check env->error_code */ diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index de63f58..f296420 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -1,15 +1,13 @@ /* * QEMU UniCore32 CPU * - * Copyright (c) 2010-2011 GUAN Xue-tao + * Copyright (c) 2010-2012 Guan Xuetao * Copyright (c) 2012 SUSE LINUX Products GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Contributions from 2012-04-01 on are considered under GPL version 2, - * or (at your option) any later version. + * published by the Free Software Foundation, or any later version. + * See the COPYING file in the top-level directory. */ #include "cpu-qom.h" @@ -32,13 +30,16 @@ static void unicore_ii_cpu_initfn(Object *obj) UniCore32CPU *cpu = UNICORE32_CPU(obj); CPUUniCore32State *env = &cpu->env; - env->cp0.c0_cpuid = 0x40010863; + env->cp0.c0_cpuid = 0x4d000863; + env->cp0.c0_cachetype = 0x0d152152; + env->cp0.c1_sys = 0x2000; + env->cp0.c2_base = 0x0; + env->cp0.c3_faultstatus = 0x0; + env->cp0.c4_faultaddr = 0x0; + env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; - env->cp0.c0_cachetype = 0x1dd20d2; - env->cp0.c1_sys = 0x00090078; } static void uc32_any_cpu_initfn(Object *obj) @@ -47,6 +48,7 @@ static void uc32_any_cpu_initfn(Object *obj) CPUUniCore32State *env = &cpu->env; env->cp0.c0_cpuid = 0xffffffff; + env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); @@ -65,8 +67,13 @@ static void uc32_cpu_initfn(Object *obj) cpu_exec_init(env); env->cpu_model_str = object_get_typename(obj); +#ifdef CONFIG_USER_ONLY env->uncached_asr = ASR_MODE_USER; env->regs[31] = 0; +#else + env->uncached_asr = ASR_MODE_PRIV; + env->regs[31] = 0x03000000; +#endif tlb_flush(env, 1); } diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 81c14ff..ff99bda 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -1,7 +1,7 @@ /* * UniCore32 virtual CPU header * - * Copyright (C) 2010-2011 GUAN Xue-tao + * Copyright (C) 2010-2012 Guan Xuetao * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -89,8 +89,10 @@ typedef struct CPUUniCore32State { #define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V) #define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV)) -#define UC32_EXCP_PRIV (ASR_MODE_PRIV) -#define UC32_EXCP_TRAP (ASR_MODE_TRAP) +#define UC32_EXCP_PRIV (1) +#define UC32_EXCP_ITRAP (2) +#define UC32_EXCP_DTRAP (3) +#define UC32_EXCP_INTR (4) /* Return the current ASR value. */ target_ulong cpu_asr_read(CPUUniCore32State *env1); @@ -120,10 +122,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask) #define UC32_HWCAP_CMOV 4 /* 1 << 2 */ #define UC32_HWCAP_UCF64 8 /* 1 << 3 */ -#define UC32_CPUID(env) (env->cp0.c0_cpuid) -#define UC32_CPUID_UCV2 0x40010863 -#define UC32_CPUID_ANY 0xffffffff - #define cpu_init uc32_cpu_init #define cpu_exec uc32_cpu_exec #define cpu_signal_handler uc32_cpu_signal_handler