diff --git a/hw/char/serial.c b/hw/char/serial.c
index f4d167f..c7a1841 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -108,8 +108,8 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 static inline void recv_fifo_put(SerialState *s, uint8_t chr)
 {
     /* Receive overruns do not overwrite FIFO contents. */
-    if (!fifo8_is_full(&s->recv_fifo)) {
-        fifo8_push(&s->recv_fifo, chr);
+    if (!fifo_is_full(&s->recv_fifo)) {
+        fifo_push8(&s->recv_fifo, chr);
     } else {
         s->lsr |= UART_LSR_OE;
     }
@@ -225,10 +225,10 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
 
     if (s->tsr_retry <= 0) {
         if (s->fcr & UART_FCR_FE) {
-            if (fifo8_is_empty(&s->xmit_fifo)) {
+            if (fifo_is_empty(&s->xmit_fifo)) {
                 return FALSE;
             }
-            s->tsr = fifo8_pop(&s->xmit_fifo);
+            s->tsr = fifo_pop8(&s->xmit_fifo);
             if (!s->xmit_fifo.num) {
                 s->lsr |= UART_LSR_THRE;
             }
@@ -284,10 +284,10 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
             s->thr = (uint8_t) val;
             if(s->fcr & UART_FCR_FE) {
                 /* xmit overruns overwrite data, so make space if needed */
-                if (fifo8_is_full(&s->xmit_fifo)) {
-                    fifo8_pop(&s->xmit_fifo);
+                if (fifo_is_full(&s->xmit_fifo)) {
+                    fifo_pop8(&s->xmit_fifo);
                 }
-                fifo8_push(&s->xmit_fifo, s->thr);
+                fifo_push8(&s->xmit_fifo, s->thr);
                 s->lsr &= ~UART_LSR_TEMT;
             }
             s->thr_ipending = 0;
@@ -334,11 +334,11 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
         if (val & UART_FCR_RFR) {
             timer_del(s->fifo_timeout_timer);
             s->timeout_ipending=0;
-            fifo8_reset(&s->recv_fifo);
+            fifo_reset(&s->recv_fifo);
         }
 
         if (val & UART_FCR_XFR) {
-            fifo8_reset(&s->xmit_fifo);
+            fifo_reset(&s->xmit_fifo);
         }
 
         if (val & UART_FCR_FE) {
@@ -427,8 +427,8 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
             ret = s->divider & 0xff;
         } else {
             if(s->fcr & UART_FCR_FE) {
-                ret = fifo8_is_empty(&s->recv_fifo) ?
-                            0 : fifo8_pop(&s->recv_fifo);
+                ret = fifo_is_empty(&s->recv_fifo) ?
+                            0 : fifo_pop8(&s->recv_fifo);
                 if (s->recv_fifo.num == 0) {
                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
                 } else {
@@ -635,8 +635,8 @@ static void serial_reset(void *opaque)
     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
     s->poll_msl = 0;
 
-    fifo8_reset(&s->recv_fifo);
-    fifo8_reset(&s->xmit_fifo);
+    fifo_reset(&s->recv_fifo);
+    fifo_reset(&s->xmit_fifo);
 
     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 
@@ -659,8 +659,8 @@ void serial_realize_core(SerialState *s, Error **errp)
 
     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
                           serial_event, s);
-    fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
-    fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
+    fifo_create(&s->recv_fifo, UART_FIFO_LENGTH);
+    fifo_create(&s->xmit_fifo, UART_FIFO_LENGTH);
 }
 
 void serial_exit_core(SerialState *s)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 469f2f0..860cb5e 100644
--- a/hw/net/allwinner_emac.c
+++ b/hw/net/allwinner_emac.c
@@ -18,7 +18,7 @@
  */
 #include "hw/sysbus.h"
 #include "net/net.h"
-#include "qemu/fifo8.h"
+#include "qemu/fifo.h"
 #include "hw/net/allwinner_emac.h"
 #include <zlib.h>
 
@@ -139,34 +139,34 @@ static void aw_emac_update_irq(AwEmacState *s)
 
 static void aw_emac_tx_reset(AwEmacState *s, int chan)
 {
-    fifo8_reset(&s->tx_fifo[chan]);
+    fifo_reset(&s->tx_fifo[chan]);
     s->tx_length[chan] = 0;
 }
 
 static void aw_emac_rx_reset(AwEmacState *s)
 {
-    fifo8_reset(&s->rx_fifo);
+    fifo_reset(&s->rx_fifo);
     s->rx_num_packets = 0;
     s->rx_packet_size = 0;
     s->rx_packet_pos = 0;
 }
 
-static void fifo8_push_word(Fifo8 *fifo, uint32_t val)
+static void fifo_push_word(Fifo *fifo, uint32_t val)
 {
-    fifo8_push(fifo, val);
-    fifo8_push(fifo, val >> 8);
-    fifo8_push(fifo, val >> 16);
-    fifo8_push(fifo, val >> 24);
+    fifo_push8(fifo, val);
+    fifo_push8(fifo, val >> 8);
+    fifo_push8(fifo, val >> 16);
+    fifo_push8(fifo, val >> 24);
 }
 
-static uint32_t fifo8_pop_word(Fifo8 *fifo)
+static uint32_t fifo_pop_word(Fifo *fifo)
 {
     uint32_t ret;
 
-    ret = fifo8_pop(fifo);
-    ret |= fifo8_pop(fifo) << 8;
-    ret |= fifo8_pop(fifo) << 16;
-    ret |= fifo8_pop(fifo) << 24;
+    ret = fifo_pop8(fifo);
+    ret |= fifo_pop8(fifo) << 8;
+    ret |= fifo_pop8(fifo) << 16;
+    ret |= fifo_pop8(fifo) << 24;
 
     return ret;
 }
@@ -179,37 +179,37 @@ static int aw_emac_can_receive(NetClientState *nc)
      * To avoid packet drops, allow reception only when there is space
      * for a full frame: 1522 + 8 (rx headers) + 2 (padding).
      */
-    return (s->ctl & EMAC_CTL_RX_EN) && (fifo8_num_free(&s->rx_fifo) >= 1532);
+    return (s->ctl & EMAC_CTL_RX_EN) && (fifo_num_free(&s->rx_fifo) >= 1532);
 }
 
 static ssize_t aw_emac_receive(NetClientState *nc, const uint8_t *buf,
                                size_t size)
 {
     AwEmacState *s = qemu_get_nic_opaque(nc);
-    Fifo8 *fifo = &s->rx_fifo;
+    Fifo *fifo = &s->rx_fifo;
     size_t padded_size, total_size;
     uint32_t crc;
 
     padded_size = size > 60 ? size : 60;
     total_size = QEMU_ALIGN_UP(RX_HDR_SIZE + padded_size + CRC_SIZE, 4);
 
-    if (!(s->ctl & EMAC_CTL_RX_EN) || (fifo8_num_free(fifo) < total_size)) {
+    if (!(s->ctl & EMAC_CTL_RX_EN) || (fifo_num_free(fifo) < total_size)) {
         return -1;
     }
 
-    fifo8_push_word(fifo, EMAC_UNDOCUMENTED_MAGIC);
-    fifo8_push_word(fifo, EMAC_RX_HEADER(padded_size + CRC_SIZE,
-                                         EMAC_RX_IO_DATA_STATUS_OK));
-    fifo8_push_all(fifo, buf, size);
+    fifo_push_word(fifo, EMAC_UNDOCUMENTED_MAGIC);
+    fifo_push_word(fifo, EMAC_RX_HEADER(padded_size + CRC_SIZE,
+                                        EMAC_RX_IO_DATA_STATUS_OK));
+    fifo_push_all(fifo, buf, size);
     crc = crc32(~0, buf, size);
 
     if (padded_size != size) {
-        fifo8_push_all(fifo, padding, padded_size - size);
+        fifo_push_all(fifo, padding, padded_size - size);
         crc = crc32(crc, padding, padded_size - size);
     }
 
-    fifo8_push_word(fifo, crc);
-    fifo8_push_all(fifo, padding, QEMU_ALIGN_UP(padded_size, 4) - padded_size);
+    fifo_push_word(fifo, crc);
+    fifo_push_all(fifo, padding, QEMU_ALIGN_UP(padded_size, 4) - padded_size);
     s->rx_num_packets++;
 
     s->int_sta |= EMAC_INT_RX;
@@ -247,7 +247,7 @@ static void aw_emac_reset(DeviceState *dev)
 static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size)
 {
     AwEmacState *s = opaque;
-    Fifo8 *fifo = &s->rx_fifo;
+    Fifo *fifo = &s->rx_fifo;
     NetClientState *nc;
     uint64_t ret;
 
@@ -267,7 +267,7 @@ static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size)
             return 0;
         }
 
-        ret = fifo8_pop_word(fifo);
+        ret = fifo_pop_word(fifo);
 
         switch (s->rx_packet_pos) {
         case 0:     /* Word is magic header */
@@ -315,7 +315,7 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value,
                           unsigned size)
 {
     AwEmacState *s = opaque;
-    Fifo8 *fifo;
+    Fifo *fifo;
     NetClientState *nc = qemu_get_queue(s->nic);
     int chan;
 
@@ -343,13 +343,13 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value,
             fifo = &s->tx_fifo[chan];
             len = s->tx_length[chan];
 
-            if (len > fifo8_num_used(fifo)) {
-                len = fifo8_num_used(fifo);
+            if (len > fifo_num_used(fifo)) {
+                len = fifo_num_used(fifo);
                 qemu_log_mask(LOG_GUEST_ERROR,
                               "allwinner_emac: TX length > fifo data length\n");
             }
             if (len > 0) {
-                data = fifo8_pop_buf(fifo, len, &ret);
+                data = fifo_pop_buf(fifo, len, &ret);
                 qemu_send_packet(nc, data, ret);
                 aw_emac_tx_reset(s, chan);
                 /* Raise TX interrupt */
@@ -374,12 +374,12 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value,
         break;
     case EMAC_TX_IO_DATA_REG:
         fifo = &s->tx_fifo[s->tx_channel];
-        if (fifo8_num_free(fifo) < 4) {
+        if (fifo_num_free(fifo) < 4) {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "allwinner_emac: TX data overruns fifo\n");
             break;
         }
-        fifo8_push_word(fifo, value);
+        fifo_push_word(fifo, value);
         break;
     case EMAC_RX_CTL_REG:
         s->rx_ctl = value;
@@ -455,9 +455,9 @@ static void aw_emac_realize(DeviceState *dev, Error **errp)
                           object_get_typename(OBJECT(dev)), dev->id, s);
     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 
-    fifo8_create(&s->rx_fifo, RX_FIFO_SIZE);
-    fifo8_create(&s->tx_fifo[0], TX_FIFO_SIZE);
-    fifo8_create(&s->tx_fifo[1], TX_FIFO_SIZE);
+    fifo_create(&s->rx_fifo, RX_FIFO_SIZE);
+    fifo_create(&s->tx_fifo[0], TX_FIFO_SIZE);
+    fifo_create(&s->tx_fifo[1], TX_FIFO_SIZE);
 }
 
 static Property aw_emac_properties[] = {
@@ -501,12 +501,12 @@ static const VMStateDescription vmstate_aw_emac = {
         VMSTATE_UINT32(int_ctl, AwEmacState),
         VMSTATE_UINT32(int_sta, AwEmacState),
         VMSTATE_UINT32(phy_target, AwEmacState),
-        VMSTATE_FIFO8(rx_fifo, AwEmacState),
+        VMSTATE_FIFO(rx_fifo, AwEmacState),
         VMSTATE_UINT32(rx_num_packets, AwEmacState),
         VMSTATE_UINT32(rx_packet_size, AwEmacState),
         VMSTATE_UINT32(rx_packet_pos, AwEmacState),
         VMSTATE_STRUCT_ARRAY(tx_fifo, AwEmacState, NUM_TX_FIFOS, 1,
-                             vmstate_fifo8, Fifo8),
+                             vmstate_fifo, Fifo),
         VMSTATE_UINT32_ARRAY(tx_length, AwEmacState, NUM_TX_FIFOS),
         VMSTATE_UINT32(tx_channel, AwEmacState),
         VMSTATE_END_OF_LIST()
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
index d44caae..ca19e47 100644
--- a/hw/ssi/xilinx_spi.c
+++ b/hw/ssi/xilinx_spi.c
@@ -27,7 +27,7 @@
 #include "hw/sysbus.h"
 #include "sysemu/sysemu.h"
 #include "qemu/log.h"
-#include "qemu/fifo8.h"
+#include "qemu/fifo.h"
 
 #include "hw/ssi.h"
 
@@ -89,15 +89,15 @@ typedef struct XilinxSPI {
 
     SSIBus *spi;
 
-    Fifo8 rx_fifo;
-    Fifo8 tx_fifo;
+    Fifo rx_fifo;
+    Fifo tx_fifo;
 
     uint32_t regs[R_MAX];
 } XilinxSPI;
 
 static void txfifo_reset(XilinxSPI *s)
 {
-    fifo8_reset(&s->tx_fifo);
+    fifo_reset(&s->tx_fifo);
 
     s->regs[R_SPISR] &= ~SR_TX_FULL;
     s->regs[R_SPISR] |= SR_TX_EMPTY;
@@ -105,7 +105,7 @@ static void txfifo_reset(XilinxSPI *s)
 
 static void rxfifo_reset(XilinxSPI *s)
 {
-    fifo8_reset(&s->rx_fifo);
+    fifo_reset(&s->rx_fifo);
 
     s->regs[R_SPISR] |= SR_RX_EMPTY;
     s->regs[R_SPISR] &= ~SR_RX_FULL;
@@ -125,8 +125,8 @@ static void xlx_spi_update_irq(XilinxSPI *s)
     uint32_t pending;
 
     s->regs[R_IPISR] |=
-            (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
-            (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
+            (!fifo_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
+            (fifo_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
 
     pending = s->regs[R_IPISR] & s->regs[R_IPIER];
 
@@ -171,16 +171,16 @@ static void spi_flush_txfifo(XilinxSPI *s)
     uint32_t tx;
     uint32_t rx;
 
-    while (!fifo8_is_empty(&s->tx_fifo)) {
-        tx = (uint32_t)fifo8_pop(&s->tx_fifo);
+    while (!fifo_is_empty(&s->tx_fifo)) {
+        tx = (uint32_t)fifo_pop8(&s->tx_fifo);
         DB_PRINT("data tx:%x\n", tx);
         rx = ssi_transfer(s->spi, tx);
         DB_PRINT("data rx:%x\n", rx);
-        if (fifo8_is_full(&s->rx_fifo)) {
+        if (fifo_is_full(&s->rx_fifo)) {
             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
         } else {
-            fifo8_push(&s->rx_fifo, (uint8_t)rx);
-            if (fifo8_is_full(&s->rx_fifo)) {
+            fifo_push8(&s->rx_fifo, (uint8_t)rx);
+            if (fifo_is_full(&s->rx_fifo)) {
                 s->regs[R_SPISR] |= SR_RX_FULL;
                 s->regs[R_IPISR] |= IRQ_DRR_FULL;
             }
@@ -205,14 +205,14 @@ spi_read(void *opaque, hwaddr addr, unsigned int size)
     addr >>= 2;
     switch (addr) {
     case R_SPIDRR:
-        if (fifo8_is_empty(&s->rx_fifo)) {
+        if (fifo_is_empty(&s->rx_fifo)) {
             DB_PRINT("Read from empty FIFO!\n");
             return 0xdeadbeef;
         }
 
         s->regs[R_SPISR] &= ~SR_RX_FULL;
-        r = fifo8_pop(&s->rx_fifo);
-        if (fifo8_is_empty(&s->rx_fifo)) {
+        r = fifo_pop8(&s->rx_fifo);
+        if (fifo_is_empty(&s->rx_fifo)) {
             s->regs[R_SPISR] |= SR_RX_EMPTY;
         }
         break;
@@ -253,8 +253,8 @@ spi_write(void *opaque, hwaddr addr,
 
     case R_SPIDTR:
         s->regs[R_SPISR] &= ~SR_TX_EMPTY;
-        fifo8_push(&s->tx_fifo, (uint8_t)value);
-        if (fifo8_is_full(&s->tx_fifo)) {
+        fifo_push8(&s->tx_fifo, (uint8_t)value);
+        if (fifo_is_full(&s->tx_fifo)) {
             s->regs[R_SPISR] |= SR_TX_FULL;
         }
         if (!spi_master_enabled(s)) {
@@ -341,8 +341,8 @@ static int xilinx_spi_init(SysBusDevice *sbd)
 
     s->irqline = -1;
 
-    fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
-    fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
+    fifo_create(&s->tx_fifo, FIFO_CAPACITY);
+    fifo_create(&s->rx_fifo, FIFO_CAPACITY);
 
     return 0;
 }
@@ -353,8 +353,8 @@ static const VMStateDescription vmstate_xilinx_spi = {
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields = (VMStateField[]) {
-        VMSTATE_FIFO8(tx_fifo, XilinxSPI),
-        VMSTATE_FIFO8(rx_fifo, XilinxSPI),
+        VMSTATE_FIFO(tx_fifo, XilinxSPI),
+        VMSTATE_FIFO(rx_fifo, XilinxSPI),
         VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
         VMSTATE_END_OF_LIST()
     }
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 8977243..5633209 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -26,7 +26,7 @@
 #include "sysemu/sysemu.h"
 #include "hw/ptimer.h"
 #include "qemu/log.h"
-#include "qemu/fifo8.h"
+#include "qemu/fifo.h"
 #include "hw/ssi.h"
 #include "qemu/bitops.h"
 
@@ -150,8 +150,8 @@ typedef struct {
     qemu_irq *cs_lines;
     SSIBus **spi;
 
-    Fifo8 rx_fifo;
-    Fifo8 tx_fifo;
+    Fifo rx_fifo;
+    Fifo tx_fifo;
 
     uint8_t num_txrx_bytes;
 
@@ -196,7 +196,7 @@ static inline int num_effective_busses(XilinxSPIPS *s)
 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field)
 {
     return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS
-                    || !fifo8_is_empty(&s->tx_fifo));
+                    || !fifo_is_empty(&s->tx_fifo));
 }
 
 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
@@ -239,9 +239,9 @@ static void xilinx_spips_update_ixr(XilinxSPIPS *s)
                                 IXR_TX_FIFO_MODE_FAIL);
     /* these are pure functions of fifo state, set them here */
     s->regs[R_INTR_STATUS] |=
-        (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
+        (fifo_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
-        (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
+        (fifo_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
     /* drive external interrupt pin */
     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
@@ -261,8 +261,8 @@ static void xilinx_spips_reset(DeviceState *d)
         s->regs[i] = 0;
     }
 
-    fifo8_reset(&s->rx_fifo);
-    fifo8_reset(&s->rx_fifo);
+    fifo_reset(&s->rx_fifo);
+    fifo_reset(&s->rx_fifo);
     /* non zero resets */
     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
@@ -315,7 +315,7 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
         uint8_t tx = 0;
         uint8_t tx_rx[num_effective_busses(s)];
 
-        if (fifo8_is_empty(&s->tx_fifo)) {
+        if (fifo_is_empty(&s->tx_fifo)) {
             if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
                 s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
             }
@@ -323,11 +323,11 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
             return;
         } else if (s->snoop_state == SNOOP_STRIPING) {
             for (i = 0; i < num_effective_busses(s); ++i) {
-                tx_rx[i] = fifo8_pop(&s->tx_fifo);
+                tx_rx[i] = fifo_pop8(&s->tx_fifo);
             }
             stripe8(tx_rx, num_effective_busses(s), false);
         } else {
-            tx = fifo8_pop(&s->tx_fifo);
+            tx = fifo_pop8(&s->tx_fifo);
             for (i = 0; i < num_effective_busses(s); ++i) {
                 tx_rx[i] = tx;
             }
@@ -339,16 +339,16 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
             DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
         }
 
-        if (fifo8_is_full(&s->rx_fifo)) {
+        if (fifo_is_full(&s->rx_fifo)) {
             s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
             DB_PRINT_L(0, "rx FIFO overflow");
         } else if (s->snoop_state == SNOOP_STRIPING) {
             stripe8(tx_rx, num_effective_busses(s), true);
             for (i = 0; i < num_effective_busses(s); ++i) {
-                fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
+                fifo_push8(&s->rx_fifo, (uint8_t)tx_rx[i]);
             }
         } else {
-           fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
+           fifo_push8(&s->rx_fifo, (uint8_t)tx_rx[0]);
         }
 
         DB_PRINT_L(debug_level, "initial snoop state: %x\n",
@@ -395,8 +395,8 @@ static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max)
 {
     int i;
 
-    for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
-        value[i] = fifo8_pop(&s->rx_fifo);
+    for (i = 0; i < max && !fifo_is_empty(&s->rx_fifo); ++i) {
+        value[i] = fifo_pop8(&s->rx_fifo);
     }
 }
 
@@ -453,12 +453,12 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 {
     int i;
-    for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
+    for (i = 0; i < num && !fifo_is_full(&s->tx_fifo); ++i) {
         if (s->regs[R_CONFIG] & ENDIAN) {
-            fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
+            fifo_push8(&s->tx_fifo, (uint8_t)(value >> 24));
             value <<= 8;
         } else {
-            fifo8_push(&s->tx_fifo, (uint8_t)value);
+            fifo_push8(&s->tx_fifo, (uint8_t)value);
             value >>= 8;
         }
     }
@@ -520,7 +520,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
 no_reg_update:
     xilinx_spips_update_cs_lines(s);
     if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
-            (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {
+            (fifo_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {
         xilinx_spips_flush_txfifo(s);
     }
     xilinx_spips_update_cs_lines(s);
@@ -580,22 +580,22 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 
         DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 
-        fifo8_reset(&s->tx_fifo);
-        fifo8_reset(&s->rx_fifo);
+        fifo_reset(&s->tx_fifo);
+        fifo_reset(&s->rx_fifo);
 
         /* instruction */
         DB_PRINT_L(0, "pushing read instruction: %02x\n",
                    (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
                                        LQSPI_CFG_INST_CODE));
-        fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
+        fifo_push8(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
         /* read address */
         DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
-        fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
-        fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
-        fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
+        fifo_push8(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
+        fifo_push8(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
+        fifo_push8(&s->tx_fifo, (uint8_t)flash_addr);
         /* mode bits */
         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
-            fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
+            fifo_push8(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
                                               LQSPI_CFG_MODE_SHIFT,
                                               LQSPI_CFG_MODE_WIDTH));
         }
@@ -603,11 +603,11 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
             DB_PRINT_L(0, "pushing dummy byte\n");
-            fifo8_push(&s->tx_fifo, 0);
+            fifo_push8(&s->tx_fifo, 0);
         }
         xilinx_spips_update_cs_lines(s);
         xilinx_spips_flush_txfifo(s);
-        fifo8_reset(&s->rx_fifo);
+        fifo_reset(&s->rx_fifo);
 
         DB_PRINT_L(0, "starting QSPI data read\n");
 
@@ -669,8 +669,8 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp)
 
     s->irqline = -1;
 
-    fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
-    fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
+    fifo_create(&s->rx_fifo, xsc->rx_fifo_size);
+    fifo_create(&s->tx_fifo, xsc->tx_fifo_size);
 }
 
 static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
@@ -707,8 +707,8 @@ static const VMStateDescription vmstate_xilinx_spips = {
     .minimum_version_id_old = 2,
     .post_load = xilinx_spips_post_load,
     .fields = (VMStateField[]) {
-        VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
-        VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
+        VMSTATE_FIFO(tx_fifo, XilinxSPIPS),
+        VMSTATE_FIFO(rx_fifo, XilinxSPIPS),
         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
         VMSTATE_END_OF_LIST()
diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h
index f431764..021499b 100644
--- a/include/hw/char/serial.h
+++ b/include/hw/char/serial.h
@@ -28,7 +28,7 @@
 #include "hw/hw.h"
 #include "sysemu/sysemu.h"
 #include "exec/memory.h"
-#include "qemu/fifo8.h"
+#include "qemu/fifo.h"
 
 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
 
@@ -60,8 +60,8 @@ struct SerialState {
 
     /* Time when the last byte was successfully sent out of the tsr */
     uint64_t last_xmit_ts;
-    Fifo8 recv_fifo;
-    Fifo8 xmit_fifo;
+    Fifo recv_fifo;
+    Fifo xmit_fifo;
     /* Interrupt trigger level for recv_fifo */
     uint8_t recv_fifo_itl;
 
diff --git a/include/hw/net/allwinner_emac.h b/include/hw/net/allwinner_emac.h
index a5e944a..295b524 100644
--- a/include/hw/net/allwinner_emac.h
+++ b/include/hw/net/allwinner_emac.h
@@ -23,7 +23,7 @@
 #define AW_EMAC_H
 
 #include "net/net.h"
-#include "qemu/fifo8.h"
+#include "qemu/fifo.h"
 
 #define TYPE_AW_EMAC "allwinner-emac"
 #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC)
@@ -197,12 +197,12 @@ typedef struct AwEmacState {
     uint32_t       int_sta;
     uint32_t       phy_target;
 
-    Fifo8          rx_fifo;
+    Fifo           rx_fifo;
     uint32_t       rx_num_packets;
     uint32_t       rx_packet_size;
     uint32_t       rx_packet_pos;
 
-    Fifo8          tx_fifo[NUM_TX_FIFOS];
+    Fifo           tx_fifo[NUM_TX_FIFOS];
     uint32_t       tx_length[NUM_TX_FIFOS];
     uint32_t       tx_channel;
 } AwEmacState;
diff --git a/include/qemu/fifo.h b/include/qemu/fifo.h
new file mode 100644
index 0000000..a704bd4
--- /dev/null
+++ b/include/qemu/fifo.h
@@ -0,0 +1,161 @@
+#ifndef FIFO_H
+#define FIFO_H
+
+#include "migration/vmstate.h"
+
+typedef struct {
+    /* All fields are private */
+    uint8_t *data;
+    uint32_t capacity;
+    uint32_t head;
+    uint32_t num;
+} Fifo;
+
+/**
+ * fifo_create:
+ * @fifo: struct Fifo to initialise with new FIFO
+ * @capacity: capacity of the newly created FIFO
+ *
+ * Create a FIFO of the specified size. Clients should call fifo_destroy()
+ * when finished using the fifo. The FIFO is initially empty.
+ */
+
+void fifo_create(Fifo *fifo, uint32_t capacity);
+
+/**
+ * fifo_destroy:
+ * @fifo: FIFO to cleanup
+ *
+ * Cleanup a FIFO created with fifo_create(). Frees memory created for FIFO
+  *storage. The FIFO is no longer usable after this has been called.
+ */
+
+void fifo_destroy(Fifo *fifo);
+
+/**
+ * fifo_push:
+ * @fifo: FIFO to push to
+ * @data: data value to push
+ *
+ * Push a data value to the FIFO. Behaviour is undefined if the FIFO is full.
+ * Clients are responsible for checking for fullness using fifo_is_full().
+ */
+
+void fifo_push8(Fifo *fifo, uint8_t data);
+
+/**
+ * fifo_push_all:
+ * @fifo: FIFO to push to
+ * @data: data to push
+ * @size: number of entries to push
+ *
+ * Push a buffer to the FIFO. Behaviour is undefined if the FIFO is full.
+ * Clients are responsible for checking the space left in the FIFO using
+ * fifo_num_free().
+ */
+
+void fifo_push_all(Fifo *fifo, const uint8_t *data, uint32_t num);
+
+/**
+ * fifo_pop:
+ * @fifo: fifo to pop from
+ *
+ * Pop a data value from the FIFO. Behaviour is undefined if the FIFO is empty.
+ * Clients are responsible for checking for emptyness using fifo_is_empty().
+ *
+ * Returns: The popped data value.
+ */
+
+uint8_t fifo_pop8(Fifo *fifo);
+
+/**
+ * fifo_pop_buf:
+ * @fifo: FIFO to pop from
+ * @max: maximum number of elements to pop
+ * @num: actual number of returned elements
+ *
+ * Pop a number of elements from the FIFO up to a maximum of max. The buffer
+ * containing the popped data is returned. This buffer points directly into
+ * the FIFO backing store and data is invalidated once any of the fifo_* APIs
+ * are called on the FIFO.
+ *
+ * The function may return fewer elements than requested when the data wraps
+ * around in the ring buffer; in this case only a contiguous part of the data
+ * is returned.
+ *
+ * The number of valid elements returned is populated in *num; will always
+ * return at least 1 element. max must not be 0 or greater than the number of
+ * elements in the FIFO.
+ *
+ * Clients are responsible for checking the availability of requested data
+ * using fifo_num_used().
+ *
+ * Returns: A pointer to popped data.
+ */
+
+const uint8_t *fifo_pop_buf(Fifo *fifo, uint32_t max, uint32_t *num);
+
+/**
+ * fifo_reset:
+ * @fifo: FIFO to reset
+ *
+ * Reset a FIFO. All data is discarded and the FIFO is emptied.
+ */
+
+void fifo_reset(Fifo *fifo);
+
+/**
+ * fifo_is_empty:
+ * @fifo: FIFO to check
+ *
+ * Check if a FIFO is empty.
+ *
+ * Returns: True if the fifo is empty, false otherwise.
+ */
+
+bool fifo_is_empty(Fifo *fifo);
+
+/**
+ * fifo_is_full:
+ * @fifo: FIFO to check
+ *
+ * Check if a FIFO is full.
+ *
+ * Returns: True if the fifo is full, false otherwise.
+ */
+
+bool fifo_is_full(Fifo *fifo);
+
+/**
+ * fifo_num_free:
+ * @fifo: FIFO to check
+ *
+ * Return the number of free elements in the FIFO.
+ *
+ * Returns: Number of free elements.
+ */
+
+uint32_t fifo_num_free(Fifo *fifo);
+
+/**
+ * fifo_num_used:
+ * @fifo: FIFO to check
+ *
+ * Return the number of used elements in the FIFO.
+ *
+ * Returns: Number of used elements.
+ */
+
+uint32_t fifo_num_used(Fifo *fifo);
+
+extern const VMStateDescription vmstate_fifo;
+
+#define VMSTATE_FIFO(_field, _state) {                               \
+    .name       = (stringify(_field)),                               \
+    .size       = sizeof(Fifo),                                      \
+    .vmsd       = &vmstate_fifo,                                     \
+    .flags      = VMS_STRUCT,                                        \
+    .offset     = vmstate_offset_value(_state, _field, Fifo),        \
+}
+
+#endif /* FIFO_H */
diff --git a/include/qemu/fifo8.h b/include/qemu/fifo8.h
deleted file mode 100644
index 8820780..0000000
--- a/include/qemu/fifo8.h
+++ /dev/null
@@ -1,160 +0,0 @@
-#ifndef FIFO_H
-#define FIFO_H
-
-#include "migration/vmstate.h"
-
-typedef struct {
-    /* All fields are private */
-    uint8_t *data;
-    uint32_t capacity;
-    uint32_t head;
-    uint32_t num;
-} Fifo8;
-
-/**
- * fifo8_create:
- * @fifo: struct Fifo8 to initialise with new FIFO
- * @capacity: capacity of the newly created FIFO
- *
- * Create a FIFO of the specified size. Clients should call fifo8_destroy()
- * when finished using the fifo. The FIFO is initially empty.
- */
-
-void fifo8_create(Fifo8 *fifo, uint32_t capacity);
-
-/**
- * fifo8_destroy:
- * @fifo: FIFO to cleanup
- *
- * Cleanup a FIFO created with fifo8_create(). Frees memory created for FIFO
-  *storage. The FIFO is no longer usable after this has been called.
- */
-
-void fifo8_destroy(Fifo8 *fifo);
-
-/**
- * fifo8_push:
- * @fifo: FIFO to push to
- * @data: data byte to push
- *
- * Push a data byte to the FIFO. Behaviour is undefined if the FIFO is full.
- * Clients are responsible for checking for fullness using fifo8_is_full().
- */
-
-void fifo8_push(Fifo8 *fifo, uint8_t data);
-
-/**
- * fifo8_push_all:
- * @fifo: FIFO to push to
- * @data: data to push
- * @size: number of bytes to push
- *
- * Push a byte array to the FIFO. Behaviour is undefined if the FIFO is full.
- * Clients are responsible for checking the space left in the FIFO using
- * fifo8_num_free().
- */
-
-void fifo8_push_all(Fifo8 *fifo, const uint8_t *data, uint32_t num);
-
-/**
- * fifo8_pop:
- * @fifo: fifo to pop from
- *
- * Pop a data byte from the FIFO. Behaviour is undefined if the FIFO is empty.
- * Clients are responsible for checking for emptyness using fifo8_is_empty().
- *
- * Returns: The popped data byte.
- */
-
-uint8_t fifo8_pop(Fifo8 *fifo);
-
-/**
- * fifo8_pop_buf:
- * @fifo: FIFO to pop from
- * @max: maximum number of bytes to pop
- * @num: actual number of returned bytes
- *
- * Pop a number of elements from the FIFO up to a maximum of max. The buffer
- * containing the popped data is returned. This buffer points directly into
- * the FIFO backing store and data is invalidated once any of the fifo8_* APIs
- * are called on the FIFO.
- *
- * The function may return fewer bytes than requested when the data wraps
- * around in the ring buffer; in this case only a contiguous part of the data
- * is returned.
- *
- * The number of valid bytes returned is populated in *num; will always return
- * at least 1 byte. max must not be 0 or greater than the number of bytes in
- * the FIFO.
- *
- * Clients are responsible for checking the availability of requested data
- * using fifo8_num_used().
- *
- * Returns: A pointer to popped data.
- */
-const uint8_t *fifo8_pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num);
-
-/**
- * fifo8_reset:
- * @fifo: FIFO to reset
- *
- * Reset a FIFO. All data is discarded and the FIFO is emptied.
- */
-
-void fifo8_reset(Fifo8 *fifo);
-
-/**
- * fifo8_is_empty:
- * @fifo: FIFO to check
- *
- * Check if a FIFO is empty.
- *
- * Returns: True if the fifo is empty, false otherwise.
- */
-
-bool fifo8_is_empty(Fifo8 *fifo);
-
-/**
- * fifo8_is_full:
- * @fifo: FIFO to check
- *
- * Check if a FIFO is full.
- *
- * Returns: True if the fifo is full, false otherwise.
- */
-
-bool fifo8_is_full(Fifo8 *fifo);
-
-/**
- * fifo8_num_free:
- * @fifo: FIFO to check
- *
- * Return the number of free bytes in the FIFO.
- *
- * Returns: Number of free bytes.
- */
-
-uint32_t fifo8_num_free(Fifo8 *fifo);
-
-/**
- * fifo8_num_used:
- * @fifo: FIFO to check
- *
- * Return the number of used bytes in the FIFO.
- *
- * Returns: Number of used bytes.
- */
-
-uint32_t fifo8_num_used(Fifo8 *fifo);
-
-extern const VMStateDescription vmstate_fifo8;
-
-#define VMSTATE_FIFO8(_field, _state) {                              \
-    .name       = (stringify(_field)),                               \
-    .size       = sizeof(Fifo8),                                     \
-    .vmsd       = &vmstate_fifo8,                                    \
-    .flags      = VMS_STRUCT,                                        \
-    .offset     = vmstate_offset_value(_state, _field, Fifo8),       \
-}
-
-#endif /* FIFO_H */
diff --git a/util/Makefile.objs b/util/Makefile.objs
index df83b62..7f1489c 100644
--- a/util/Makefile.objs
+++ b/util/Makefile.objs
@@ -3,7 +3,7 @@ util-obj-$(CONFIG_WIN32) += oslib-win32.o qemu-thread-win32.o event_notifier-win
 util-obj-$(CONFIG_POSIX) += oslib-posix.o qemu-thread-posix.o event_notifier-posix.o qemu-openpty.o
 util-obj-y += envlist.o path.o host-utils.o cache-utils.o module.o
 util-obj-y += bitmap.o bitops.o hbitmap.o
-util-obj-y += fifo8.o
+util-obj-y += fifo.o
 util-obj-y += acl.o
 util-obj-y += error.o qemu-error.o
 util-obj-$(CONFIG_POSIX) += compatfd.o
diff --git a/util/fifo8.c b/util/fifo.c
similarity index 75%
rename from util/fifo8.c
rename to util/fifo.c
index 6a43482..4ee6c85 100644
--- a/util/fifo8.c
+++ b/util/fifo.c
@@ -13,9 +13,9 @@
  */
 
 #include "qemu-common.h"
-#include "qemu/fifo8.h"
+#include "qemu/fifo.h"
 
-void fifo8_create(Fifo8 *fifo, uint32_t capacity)
+void fifo_create(Fifo *fifo, uint32_t capacity)
 {
     fifo->data = g_new(uint8_t, capacity);
     fifo->capacity = capacity;
@@ -23,12 +23,12 @@ void fifo8_create(Fifo8 *fifo, uint32_t capacity)
     fifo->num = 0;
 }
 
-void fifo8_destroy(Fifo8 *fifo)
+void fifo_destroy(Fifo *fifo)
 {
     g_free(fifo->data);
 }
 
-void fifo8_push(Fifo8 *fifo, uint8_t data)
+void fifo_push8(Fifo *fifo, uint8_t data)
 {
     if (fifo->num == fifo->capacity) {
         abort();
@@ -37,7 +37,7 @@ void fifo8_push(Fifo8 *fifo, uint8_t data)
     fifo->num++;
 }
 
-void fifo8_push_all(Fifo8 *fifo, const uint8_t *data, uint32_t num)
+void fifo_push_all(Fifo *fifo, const uint8_t *data, uint32_t num)
 {
     uint32_t start, avail;
 
@@ -58,7 +58,7 @@ void fifo8_push_all(Fifo8 *fifo, const uint8_t *data, uint32_t num)
     fifo->num += num;
 }
 
-uint8_t fifo8_pop(Fifo8 *fifo)
+uint8_t fifo_pop8(Fifo *fifo)
 {
     uint8_t ret;
 
@@ -71,7 +71,7 @@ uint8_t fifo8_pop(Fifo8 *fifo)
     return ret;
 }
 
-const uint8_t *fifo8_pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num)
+const uint8_t *fifo_pop_buf(Fifo *fifo, uint32_t max, uint32_t *num)
 {
     uint8_t *ret;
 
@@ -86,41 +86,41 @@ const uint8_t *fifo8_pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num)
     return ret;
 }
 
-void fifo8_reset(Fifo8 *fifo)
+void fifo_reset(Fifo *fifo)
 {
     fifo->num = 0;
     fifo->head = 0;
 }
 
-bool fifo8_is_empty(Fifo8 *fifo)
+bool fifo_is_empty(Fifo *fifo)
 {
     return (fifo->num == 0);
 }
 
-bool fifo8_is_full(Fifo8 *fifo)
+bool fifo_is_full(Fifo *fifo)
 {
     return (fifo->num == fifo->capacity);
 }
 
-uint32_t fifo8_num_free(Fifo8 *fifo)
+uint32_t fifo_num_free(Fifo *fifo)
 {
     return fifo->capacity - fifo->num;
 }
 
-uint32_t fifo8_num_used(Fifo8 *fifo)
+uint32_t fifo_num_used(Fifo *fifo)
 {
     return fifo->num;
 }
 
-const VMStateDescription vmstate_fifo8 = {
+const VMStateDescription vmstate_fifo = {
     .name = "Fifo8",
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField[]) {
-        VMSTATE_VBUFFER_UINT32(data, Fifo8, 1, NULL, 0, capacity),
-        VMSTATE_UINT32(head, Fifo8),
-        VMSTATE_UINT32(num, Fifo8),
+        VMSTATE_VBUFFER_UINT32(data, Fifo, 1, NULL, 0, capacity),
+        VMSTATE_UINT32(head, Fifo),
+        VMSTATE_UINT32(num, Fifo),
         VMSTATE_END_OF_LIST()
     }
 };
