diff --git a/linux-user/main.c b/linux-user/main.c
index 3f32db0..a113e87 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2888,7 +2888,7 @@ void cpu_loop(CPUMBState *env)
 	case EXCP_INTERRUPT:
 	  /* just indicate that signals should be handled asap */
 	  break;
-        case EXCP_BREAK:
+        case MB_EXCP_BREAK:
             /* Return address is 4 bytes after the call.  */
             env->regs[14] += 4;
             env->sregs[SR_PC] = env->regs[14];
@@ -2903,7 +2903,7 @@ void cpu_loop(CPUMBState *env)
                              0, 0);
             env->regs[3] = ret;
             break;
-        case EXCP_HW_EXCP:
+        case MB_EXCP_HW_EXCP:
             env->regs[17] = env->sregs[SR_PC] + 4;
             if (env->iflags & D_FLAG) {
                 env->sregs[SR_ESR] |= 1 << 12;
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index ff38661..ba02a87 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -36,11 +36,11 @@ typedef struct CPUMBState CPUMBState;
 
 #define ELF_MACHINE	EM_MICROBLAZE
 
-#define EXCP_MMU        1
-#define EXCP_IRQ        2
-#define EXCP_BREAK      3
-#define EXCP_HW_BREAK   4
-#define EXCP_HW_EXCP    5
+#define MB_EXCP_MMU        1
+#define MB_EXCP_IRQ        2
+#define MB_EXCP_BREAK      3
+#define MB_EXCP_HW_BREAK   4
+#define MB_EXCP_HW_EXCP    5
 
 /* MicroBlaze-specific interrupt pending bits.  */
 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 839680b..2f45d38 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -97,12 +97,12 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
                     break;
             }
 
-            if (cs->exception_index == EXCP_MMU) {
+            if (cs->exception_index == MB_EXCP_MMU) {
                 cpu_abort(cs, "recursive faults\n");
             }
 
             /* TLB miss.  */
-            cs->exception_index = EXCP_MMU;
+            cs->exception_index = MB_EXCP_MMU;
         }
     } else {
         /* MMU disabled or not available.  */
@@ -126,7 +126,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
 /*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
     env->res_addr = RES_ADDR_NONE;
     switch (cs->exception_index) {
-        case EXCP_HW_EXCP:
+        case MB_EXCP_HW_EXCP:
             if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
                 qemu_log("Exception raised on system without exceptions!\n");
                 return;
@@ -157,7 +157,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
             env->sregs[SR_PC] = cpu->base_vectors + 0x20;
             break;
 
-        case EXCP_MMU:
+        case MB_EXCP_MMU:
             env->regs[17] = env->sregs[SR_PC];
 
             env->sregs[SR_ESR] &= ~(1 << 12);
@@ -197,7 +197,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
             env->sregs[SR_PC] = cpu->base_vectors + 0x20;
             break;
 
-        case EXCP_IRQ:
+        case MB_EXCP_IRQ:
             assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
             assert(env->sregs[SR_MSR] & MSR_IE);
             assert(!(env->iflags & D_FLAG));
@@ -239,8 +239,8 @@ void mb_cpu_do_interrupt(CPUState *cs)
             //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
             break;
 
-        case EXCP_BREAK:
-        case EXCP_HW_BREAK:
+        case MB_EXCP_BREAK:
+        case MB_EXCP_HW_BREAK:
             assert(!(env->iflags & IMM_FLAG));
             assert(!(env->iflags & D_FLAG));
             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
@@ -251,7 +251,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
             env->sregs[SR_MSR] |= t;
             env->sregs[SR_MSR] |= MSR_BIP;
-            if (cs->exception_index == EXCP_HW_BREAK) {
+            if (cs->exception_index == MB_EXCP_HW_BREAK) {
                 env->regs[16] = env->sregs[SR_PC];
                 env->sregs[SR_MSR] |= MSR_BIP;
                 env->sregs[SR_PC] = cpu->base_vectors + 0x18;
@@ -296,7 +296,7 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
         && (env->sregs[SR_MSR] & MSR_IE)
         && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
         && !(env->iflags & (D_FLAG | IMM_FLAG))) {
-        cs->exception_index = EXCP_IRQ;
+        cs->exception_index = MB_EXCP_IRQ;
         mb_cpu_do_interrupt(cs);
         return true;
     }
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index a4c8f04..1e7db6a 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -164,7 +164,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
         if ((env->sregs[SR_MSR] & MSR_EE)
             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
-            helper_raise_exception(env, EXCP_HW_EXCP);
+            helper_raise_exception(env, MB_EXCP_HW_EXCP);
         }
         return 0;
     }
@@ -192,7 +192,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
 static void raise_fpu_exception(CPUMBState *env)
 {
     env->sregs[SR_ESR] = ESR_EC_FPU;
-    helper_raise_exception(env, EXCP_HW_EXCP);
+    helper_raise_exception(env, MB_EXCP_HW_EXCP);
 }
 
 static void update_fpu_flags(CPUMBState *env, int flags)
@@ -461,7 +461,7 @@ void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
             if (!(env->sregs[SR_MSR] & MSR_EE)) {
                 return;
             }
-            helper_raise_exception(env, EXCP_HW_EXCP);
+            helper_raise_exception(env, MB_EXCP_HW_EXCP);
     }
 }
 
@@ -472,7 +472,7 @@ void helper_stackprot(CPUMBState *env, uint32_t addr)
                      addr, env->slr, env->shr);
             env->sregs[SR_EAR] = addr;
             env->sregs[SR_ESR] = ESR_EC_STACKPROT;
-            helper_raise_exception(env, EXCP_HW_EXCP);
+            helper_raise_exception(env, MB_EXCP_HW_EXCP);
     }
 }
 
@@ -510,12 +510,12 @@ void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
     if (is_exec) {
         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
-            helper_raise_exception(env, EXCP_HW_EXCP);
+            helper_raise_exception(env, MB_EXCP_HW_EXCP);
         }
     } else {
         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
-            helper_raise_exception(env, EXCP_HW_EXCP);
+            helper_raise_exception(env, MB_EXCP_HW_EXCP);
         }
     }
 }
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 14e7a31..b199d1d 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -324,7 +324,7 @@ static void dec_pattern(DisasContext *dc)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
           && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
     }
 
     mode = dc->opcode & 3;
@@ -461,7 +461,7 @@ static void dec_msr(DisasContext *dc)
         if ((dc->tb_flags & MSR_EE_FLAG)
             && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
             tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-            t_gen_raise_exception(dc, EXCP_HW_EXCP);
+            t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
             return;
         }
 
@@ -490,7 +490,7 @@ static void dec_msr(DisasContext *dc)
         if ((dc->tb_flags & MSR_EE_FLAG)
              && mem_index == MMU_USER_IDX) {
             tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-            t_gen_raise_exception(dc, EXCP_HW_EXCP);
+            t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
             return;
         }
     }
@@ -641,7 +641,7 @@ static void dec_mul(DisasContext *dc)
          && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
          && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         return;
     }
 
@@ -698,7 +698,7 @@ static void dec_div(DisasContext *dc)
     if ((dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
           && !((dc->cpu->env.pvr.regs[0] & PVR0_USE_DIV_MASK))) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
     }
 
     if (u)
@@ -720,7 +720,7 @@ static void dec_barrel(DisasContext *dc)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
           && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         return;
     }
 
@@ -799,7 +799,7 @@ static void dec_bit(DisasContext *dc)
             if ((dc->tb_flags & MSR_EE_FLAG)
                  && mem_index == MMU_USER_IDX) {
                 tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-                t_gen_raise_exception(dc, EXCP_HW_EXCP);
+                t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
                 return;
             }
             break;
@@ -809,7 +809,7 @@ static void dec_bit(DisasContext *dc)
             if ((dc->tb_flags & MSR_EE_FLAG)
                  && mem_index == MMU_USER_IDX) {
                 tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-                t_gen_raise_exception(dc, EXCP_HW_EXCP);
+                t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
                 return;
             }
             break;
@@ -818,7 +818,7 @@ static void dec_bit(DisasContext *dc)
                 && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
                 && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
                 tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-                t_gen_raise_exception(dc, EXCP_HW_EXCP);
+                t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
             }
             if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
                 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
@@ -931,7 +931,7 @@ static void dec_load(DisasContext *dc)
     if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         return;
     }
 
@@ -1064,7 +1064,7 @@ static void dec_store(DisasContext *dc)
     if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         return;
     }
 
@@ -1301,11 +1301,11 @@ static void dec_br(DisasContext *dc)
         tcg_gen_mov_i32(env_btarget, *(dec_alu_op_b(dc)));
         if (link && !dslot) {
             if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
-                t_gen_raise_exception(dc, EXCP_BREAK);
+                t_gen_raise_exception(dc, MB_EXCP_BREAK);
             if (dc->imm == 0) {
                 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
                     tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-                    t_gen_raise_exception(dc, EXCP_HW_EXCP);
+                    t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
                     return;
                 }
 
@@ -1396,7 +1396,7 @@ static void dec_rts(DisasContext *dc)
         if ((dc->tb_flags & MSR_EE_FLAG)
              && mem_index == MMU_USER_IDX) {
             tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-            t_gen_raise_exception(dc, EXCP_HW_EXCP);
+            t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         }
         dc->tb_flags |= DRTI_FLAG;
     } else if (b_bit) {
@@ -1404,7 +1404,7 @@ static void dec_rts(DisasContext *dc)
         if ((dc->tb_flags & MSR_EE_FLAG)
              && mem_index == MMU_USER_IDX) {
             tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-            t_gen_raise_exception(dc, EXCP_HW_EXCP);
+            t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         }
         dc->tb_flags |= DRTB_FLAG;
     } else if (e_bit) {
@@ -1412,7 +1412,7 @@ static void dec_rts(DisasContext *dc)
         if ((dc->tb_flags & MSR_EE_FLAG)
              && mem_index == MMU_USER_IDX) {
             tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-            t_gen_raise_exception(dc, EXCP_HW_EXCP);
+            t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         }
         dc->tb_flags |= DRTE_FLAG;
     } else
@@ -1431,7 +1431,7 @@ static int dec_check_fpuv2(DisasContext *dc)
 
     if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_FPU);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
     }
     return r;
 }
@@ -1444,7 +1444,7 @@ static void dec_fpu(DisasContext *dc)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
           && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         return;
     }
 
@@ -1546,7 +1546,7 @@ static void dec_null(DisasContext *dc)
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         return;
     }
     qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
@@ -1565,7 +1565,7 @@ static void dec_stream(DisasContext *dc)
 
     if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
         tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
-        t_gen_raise_exception(dc, EXCP_HW_EXCP);
+        t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
         return;
     }
 
@@ -1635,7 +1635,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
               && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
               && (dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
             tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
-            t_gen_raise_exception(dc, EXCP_HW_EXCP);
+            t_gen_raise_exception(dc, MB_EXCP_HW_EXCP);
             return;
         }
 
