From patchwork Mon Oct 18 03:17:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 68118 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 98ADAB70EF for ; Mon, 18 Oct 2010 15:07:38 +1100 (EST) Received: from [127.0.0.1] (port=54443 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P7gPA-0005ez-0R for incoming@patchwork.ozlabs.org; Sun, 17 Oct 2010 23:28:56 -0400 Received: from [140.186.70.92] (port=51827 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P7gEg-0002Y3-G2 for qemu-devel@nongnu.org; Sun, 17 Oct 2010 23:18:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P7gEd-00044F-Rc for qemu-devel@nongnu.org; Sun, 17 Oct 2010 23:18:06 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:50716) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P7gEd-00043a-J4 for qemu-devel@nongnu.org; Sun, 17 Oct 2010 23:18:03 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 05EF1188E8; Mon, 18 Oct 2010 12:17:59 +0900 (JST) Received: (nullmailer pid 16510 invoked by uid 1000); Mon, 18 Oct 2010 03:17:56 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Mon, 18 Oct 2010 12:17:46 +0900 Message-Id: <67902bbeea8ed4f7b776c1ea9f0d585a2374eb37.1287371107.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v4 05/15] pci/bridge: fix pci_bridge_reset() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org lower 4bits of base/limit register is RO, and should not be modified on reset. Signed-off-by: Isaku Yamahata --- hw/pci_bridge.c | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c index 638e3b3..7229610 100644 --- a/hw/pci_bridge.c +++ b/hw/pci_bridge.c @@ -161,12 +161,15 @@ void pci_bridge_reset_reg(PCIDevice *dev) conf[PCI_SUBORDINATE_BUS] = 0; conf[PCI_SEC_LATENCY_TIMER] = 0; - conf[PCI_IO_BASE] = 0; - conf[PCI_IO_LIMIT] = 0; - pci_set_word(conf + PCI_MEMORY_BASE, 0); - pci_set_word(conf + PCI_MEMORY_LIMIT, 0); - pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0); - pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0); + pci_clear_bit_byte(conf + PCI_IO_BASE, PCI_IO_RANGE_MASK & 0xff); + pci_clear_bit_byte(conf + PCI_IO_LIMIT, PCI_IO_RANGE_MASK & 0xff); + pci_clear_bit_word(conf + PCI_MEMORY_BASE, PCI_MEMORY_RANGE_MASK & 0xffff); + pci_clear_bit_word(conf + PCI_MEMORY_LIMIT, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_clear_bit_word(conf + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_MASK & 0xffff); + pci_clear_bit_word(conf + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_MASK & 0xffff); pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);