From patchwork Thu Oct 28 19:27:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 1547674 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgH86385lz9sX3 for ; Fri, 29 Oct 2021 07:23:50 +1100 (AEDT) Received: from localhost ([::1]:33194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgBwC-0005F8-3F for incoming@patchwork.ozlabs.org; Thu, 28 Oct 2021 16:23:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgBWe-0003fF-8k for qemu-devel@nongnu.org; Thu, 28 Oct 2021 15:57:25 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:64535) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgBWX-0000PF-Qn for qemu-devel@nongnu.org; Thu, 28 Oct 2021 15:57:23 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 61D707561A5; Thu, 28 Oct 2021 21:57:06 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id A00C67561C4; Thu, 28 Oct 2021 21:57:05 +0200 (CEST) Message-Id: <647c291f53b4de0e79b979aaeee761ec4cf01a20.1635449225.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v4 20/23] hw/timer/sh_timer: Rename sh_timer_state to SHTimerState Date: Thu, 28 Oct 2021 21:27:05 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Magnus Damm , Yoshinori Sato Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" According to coding style types should be camel case, also remove unneded casts from void *. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé --- The tmu123_state is left for now, that's the real exported object with SHTimerState being an internal object for a single timer. I'll come back to this when QOM-ifying so only handled SHTimerState in this patch. hw/timer/sh_timer.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index e1b6145df8..2038adfb0a 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -45,11 +45,11 @@ typedef struct { int feat; int enabled; qemu_irq irq; -} sh_timer_state; +} SHTimerState; /* Check all active timers, and schedule the next timer interrupt. */ -static void sh_timer_update(sh_timer_state *s) +static void sh_timer_update(SHTimerState *s) { int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); @@ -62,7 +62,7 @@ static void sh_timer_update(sh_timer_state *s) static uint32_t sh_timer_read(void *opaque, hwaddr offset) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; switch (offset >> 2) { case OFFSET_TCOR: @@ -85,7 +85,7 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset) static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; int freq; switch (offset >> 2) { @@ -200,7 +200,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, static void sh_timer_start_stop(void *opaque, int enable) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; trace_sh_timer_start_stop(enable, s->enabled); ptimer_transaction_begin(s->timer); @@ -216,14 +216,14 @@ static void sh_timer_start_stop(void *opaque, int enable) static void sh_timer_tick(void *opaque) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; s->int_level = s->enabled; sh_timer_update(s); } static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) { - sh_timer_state *s; + SHTimerState *s; s = g_malloc0(sizeof(*s)); s->freq = freq; @@ -259,7 +259,7 @@ typedef struct { static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size) { - tmu012_state *s = (tmu012_state *)opaque; + tmu012_state *s = opaque; trace_sh_timer_read(offset); if (offset >= 0x20) { @@ -289,7 +289,7 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, static void tmu012_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - tmu012_state *s = (tmu012_state *)opaque; + tmu012_state *s = opaque; trace_sh_timer_write(offset, value); if (offset >= 0x20) {